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(parent: 32b2d75) | patch
target/riscv KVM_RISCV_SET_TIMER macro is not configured correctly
authoryang.zhang <yang.zhang@hexintek.com>
Fri, 7 Jul 2023 03:23:06 +0000 (11:23 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 10 Jul 2023 12:29:15 +0000 (22:29 +1000)
commitc5cc248b478bc21e50845ba6b2414c4a688e195f
tree446e7ba209b478a4f4a2cc7516d6312802748451tree
parent32b2d75bf7fab6fa82dd01b2413ca14753b90973commit | diff
target/riscv KVM_RISCV_SET_TIMER macro is not configured correctly

Should set/get riscv all reg timer,i.e, time/compare/frequency/state.

Signed-off-by: Yang Zhang <yang.zhang@hexintek.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1688
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230707032306.4606-1-gaoshanliukou@163.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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