]> git.proxmox.com Git - mirror_ubuntu-kernels.git/commit
coresight tmc etr: Cleanup AXICTL register handling
authorSuzuki K Poulose <suzuki.poulose@arm.com>
Wed, 2 Aug 2017 16:22:14 +0000 (10:22 -0600)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Mon, 28 Aug 2017 14:05:49 +0000 (16:05 +0200)
commitcd407abd5efd6f36b6372d615fbab486936e90f4
tree1f2f04f34ef21401c540b622c7dfec93e424d655
parentff11f5bc5a42f2cfc9705481eedf1b4d470ade2c
coresight tmc etr: Cleanup AXICTL register handling

This patch cleans up how we setup the AXICTL register on
TMC ETR. At the moment we don't set the CacheCtrl bits, which
drives the arcache and awcache bits on AXI bus specifying the
cacheablitiy. Set this to Write-back Read and Write-allocate.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/hwtracing/coresight/coresight-tmc-etr.c
drivers/hwtracing/coresight/coresight-tmc.h