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(parent: adc370a) | patch
target-mips: add ERETNC instruction and Config5.LLB bit
authorLeon Alrae <leon.alrae@imgtec.com>
Thu, 4 Jun 2015 16:00:31 +0000 (17:00 +0100)
committerLeon Alrae <leon.alrae@imgtec.com>
Thu, 11 Jun 2015 09:13:29 +0000 (10:13 +0100)
commitce9782f40ac16660ea9437bfaa2c9c34d5ed8110
tree359405ef71ce11ab76a77c82450f9af82f0c687etree
parentadc370a48fd26b92188fa4848dfb088578b1936ccommit | diff
target-mips: add ERETNC instruction and Config5.LLB bit

ERETNC is identical to ERET except that an ERETNC will not clear the LLbit
that is set by execution of an LL instruction, and thus when placed between
an LL and SC sequence, will never cause the SC to fail.

Presence of ERETNC is denoted by the Config5.LLB.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
disas/mips.c diff | blob | blame | history
target-mips/cpu.h diff | blob | blame | history
target-mips/helper.h diff | blob | blame | history
target-mips/op_helper.c diff | blob | blame | history
target-mips/translate.c diff | blob | blame | history
target-mips/translate_init.c diff | blob | blame | history
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