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(parent: 16c6c80) | patch
xilinx_axienet: Implement R_IS behaviour
authorPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Wed, 5 Dec 2012 06:53:42 +0000 (16:53 +1000)
committerEdgar E. Iglesias <edgar.iglesias@gmail.com>
Wed, 5 Dec 2012 08:20:36 +0000 (09:20 +0100)
commitd4d230da08918183929c7d6cb54824b391536904
tree20778c617d57e72f4988c12d7a7bc448108d8361tree
parent16c6c80ac3a772b42a87b77dfdf0fdac7c607b0ecommit | diff
xilinx_axienet: Implement R_IS behaviour

The interrupt status register R_IS is the standard clear-on-write behaviour.
This was unimplemented and defaulting to updating the register to the written
value. Implemented clear-on-write.

Reported-by: Jason Wu <huanyu@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
hw/xilinx_axienet.c diff | blob | blame | history
Qemu copy for testing