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(parent: 2df6c2d) | patch
sparc64: interrupt trap handling
authorIgor V. Kovalenko <igor.v.kovalenko@gmail.com>
Thu, 7 Jan 2010 20:28:31 +0000 (23:28 +0300)
committerBlue Swirl <blauwirbel@gmail.com>
Fri, 8 Jan 2010 17:25:13 +0000 (17:25 +0000)
commitd532b26c9dee0fb5b2186572f921b1e413963ec2
tree75eef4cbe9034f96b98c176db0e8eeb03923f652tree
parent2df6c2d0de31461f18d97f8a4d122bdb003297dbcommit | diff
sparc64: interrupt trap handling

cpu_check_irqs
- handle SOFTINT register TICK and STICK timer bits
- only check interrupt levels greater than PIL value
- handle preemption by higher level traps

cpu_exec
- handle CPU_INTERRUPT_HARD only if interrupts are enabled
- PIL 15 is not special level on sparcv9

Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
cpu-exec.c diff | blob | blame | history
hw/sun4u.c diff | blob | blame | history
target-sparc/cpu.h diff | blob | blame | history
Qemu copy for testing