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(parent: 2704cf5) | patch
drm/i915: Flush other plane register writes
authorKeith Packard <keithp@keithp.com>
Thu, 28 Jul 2011 21:47:14 +0000 (14:47 -0700)
committerKeith Packard <keithp@keithp.com>
Thu, 28 Jul 2011 23:28:35 +0000 (16:28 -0700)
commitd74362c9e45689d8d7e3d4bcf6681c4358ef4f2e
treefca86658c69f3a778e1eb39ca58b983c5b36140etree
parent2704cf5fbd248871a745d210733c6319959d2b0ccommit | diff
drm/i915: Flush other plane register writes

Writes to the plane control register are buffered in the chip until a
write to the DSPADDR (pre-965) or DSPSURF (post-965) register occurs.

This patch adds flushes in:

intel_enable_plane
gen6_init_clock_gating
ivybridge_init_clock_gating

Signed-off-by: Keith Packard <keithp@keithp.com>
drivers/gpu/drm/i915/intel_display.c diff | blob | blame | history
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