* Incorrect divider setting
* Cruft written to the clock registers (seemingly harmless but Not
Good (tm))
It also eliminates some unnecessary ifs and tidies the loop syntax.
Thanks to Philipp Zabel who discovered the divider issue, commenting
"Except for the SDCLK = HCLK (divider bypassed) case, the clock
setting resulted in double the requested frequency.
The smallest possible frequency (f_max/512) is configured with
a divider setting 0x80, not 0x40."
Signed-off-by: Ian Molton <ian@mnementh.co.uk> Signed-off-by: Pierre Ossman <pierre@ossman.eu>