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drm/amdgpu: used cached gca values for vi_read_register (v2)
authorAlex Deucher <alexander.deucher@amd.com>
Mon, 10 Oct 2016 16:05:32 +0000 (12:05 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 25 Oct 2016 18:38:32 +0000 (14:38 -0400)
commitdb9635cc14f316346c5b3954153d7e8c7016105d
tree2ee8ec2d421def4a79eaa1bad0d3e478ba9b49detree
parent34817db6c73d110d460daf02b977f583caa05a97commit | diff
drm/amdgpu: used cached gca values for vi_read_register (v2)

Using the cached values has less latency for bare metal
and SR-IOV, and prevents reading back bogus values if the
engine is powergated.

v2: fix typo in tile idx calculation

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/vi.c diff | blob | blame | history
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