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x86/mce: Add Xeon Icelake to list of CPUs that support PPIN
authorTony Luck <tony.luck@intel.com>
Mon, 28 Oct 2019 16:37:19 +0000 (09:37 -0700)
committerBorislav Petkov <bp@suse.de>
Fri, 1 Nov 2019 16:29:36 +0000 (17:29 +0100)
commitdc6b025de95bcd22ff37c4fabb022ec8a027abf1
treea386a4d78a55c5bac68cb145d92798bcba3e1487tree
parent9c3bafaa1fd88e4dd2dba3735a1f1abb0f2c7bb7commit | diff
x86/mce: Add Xeon Icelake to list of CPUs that support PPIN

New CPU model, same MSRs to control and read the inventory number.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/20191028163719.19708-1-tony.luck@intel.com
arch/x86/kernel/cpu/mce/intel.c diff | blob | blame | history
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