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drm/amdgpu: Hardcode reg access using L1 security
authorTrigger Huang <Trigger.Huang@amd.com>
Mon, 3 Jun 2019 08:48:17 +0000 (16:48 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 11 Jun 2019 17:39:51 +0000 (12:39 -0500)
commite0301317acfed896c3bcbcbdf33f67f55c9d602b
tree76764f8fd4eedc65469d6b681244ead788e2787ctree
parente038b9016aa88a9e1429f1b016644c509b8e58a6commit | diff
drm/amdgpu: Hardcode reg access using L1 security

Under Vega10 SR-IOV VF, L1 register access mode should be enabled by
default as the non-security VF will no longer be supported.

Signed-off-by: Trigger Huang <Trigger.Huang@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c diff | blob | blame | history
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