]> git.proxmox.com Git - mirror_qemu.git/commit
hw/intc: Make RISC-V ACLINT mtime MMIO register writable
authorFrank Chang <frank.chang@sifive.com>
Wed, 20 Apr 2022 08:08:59 +0000 (16:08 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 22 Apr 2022 00:35:16 +0000 (10:35 +1000)
commite2f01f3c2e13bfe0d143d960e784909d924640f3
tree535e6a7ec01754d00785db96d2509fa80dc2db44
parentd42df0ea5dd58cfda5e1466487f93b5b90a67594
hw/intc: Make RISC-V ACLINT mtime MMIO register writable

RISC-V privilege spec defines that mtime is exposed as a memory-mapped
machine-mode read-write register. However, as QEMU uses host monotonic
timer as timer source, this makes mtime to be read-only in RISC-V
ACLINT.

This patch makes mtime to be writable by recording the time delta value
between the mtime value to be written and the timer value at the time
mtime is written. Time delta value is then added back whenever the timer
value is retrieved.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220420080901.14655-4-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
hw/intc/riscv_aclint.c
include/hw/intc/riscv_aclint.h
target/riscv/cpu.h
target/riscv/cpu_helper.c