]> git.proxmox.com Git - mirror_ubuntu-kernels.git/commit
drm/i915/pvc: Annotate two more workaround/tuning registers as MCR
authorMatt Roper <matthew.d.roper@intel.com>
Wed, 1 Feb 2023 22:28:28 +0000 (14:28 -0800)
committerJani Nikula <jani.nikula@intel.com>
Wed, 15 Feb 2023 15:33:07 +0000 (17:33 +0200)
commiteffc0905d741b4138806747407baf8de98390c72
tree8acb5cd885c3893704da5e7f42eb84156321b2ae
parenteb66553d356b44c08db56fd5ecea162cfe4bf8fd
drm/i915/pvc: Annotate two more workaround/tuning registers as MCR

XEHPC_LNCFMISCCFGREG0 and XEHPC_L3SCRUB are both in MCR register ranges
on PVC (with HALFBSLICE and L3BANK replication respectively), so they
should be explicitly declared as MCR registers and use MCR-aware
workaround handlers.

The workarounds/tuning settings should still be applied properly on PVC
even without the MCR annotation, but readback verification on
CONFIG_DRM_I915_DEBUG_GEM builds could potentitally give false positive
"workaround lost on load" warnings on parts fused such that a unicast
read targets a terminated register instance.

Fixes: a9e69428b1b4 ("drm/i915: Define MCR registers explicitly")
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230201222831.608281-1-matthew.d.roper@intel.com
(cherry picked from commit 4039e44237e8ebb06f0e4af549fbedf7c41df9db)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/gt/intel_gt_regs.h
drivers/gpu/drm/i915/gt/intel_workarounds.c