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target/loongarch: Add LoongArch IOCSR instruction
authorXiaojuan Yang <yangxiaojuan@loongson.cn>
Mon, 6 Jun 2022 12:43:16 +0000 (20:43 +0800)
committerRichard Henderson <richard.henderson@linaro.org>
Mon, 6 Jun 2022 18:09:03 +0000 (18:09 +0000)
commitf84a2aacf5d1679b1d1cceabb6006e02864232f3
tree7ab99d30271e045fd93932c599aa8d6901aa54aetree
parent5b1dedfe848b61521aa5b46b81a4cc676e9e7c1bcommit | diff
target/loongarch: Add LoongArch IOCSR instruction

This includes:
- IOCSR{RD/WR}.{B/H/W/D}

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-27-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/loongarch/cpu.c diff | blob | blame | history
target/loongarch/cpu.h diff | blob | blame | history
target/loongarch/disas.c diff | blob | blame | history
target/loongarch/helper.h diff | blob | blame | history
target/loongarch/insn_trans/trans_privileged.c.inc diff | blob | blame | history
target/loongarch/insns.decode diff | blob | blame | history
target/loongarch/iocsr_helper.c [new file with mode: 0644] blob
target/loongarch/meson.build diff | blob | blame | history
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