]> git.proxmox.com Git - mirror_qemu.git/commit
target/riscv: Add Zvknh ISA extension support
authorKiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Tue, 11 Jul 2023 16:59:09 +0000 (00:59 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 11 Sep 2023 01:45:55 +0000 (11:45 +1000)
commitfcf1943376a50a26382143da5f886609c0619d44
tree9000688998f83dbf1068bf09b8c5568df7003576
parente972bf22f6f00a1a145a2e2285095aa180beb143
target/riscv: Add Zvknh ISA extension support

This commit adds support for the Zvknh vector-crypto extension, which
consists of the following instructions:

* vsha2ms.vv
* vsha2c[hl].vv

Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.

Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
[max.chou@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
[max.chou@sifive.com: Exposed x-zvknha & x-zvknhb properties]
[max.chou@sifive.com: Replaced SEW selection to happened during
translation]
Message-ID: <20230711165917.2629866-11-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu_cfg.h
target/riscv/helper.h
target/riscv/insn32.decode
target/riscv/insn_trans/trans_rvvk.c.inc
target/riscv/vcrypto_helper.c