]> git.proxmox.com Git - mirror_qemu.git/commit
target/riscv: rvv: Add mask agnostic for vector integer shift instructions
authorYueh-Ting (eop) Chen <eop.chen@sifive.com>
Mon, 20 Jun 2022 06:50:58 +0000 (06:50 +0000)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 7 Sep 2022 07:18:33 +0000 (09:18 +0200)
commitfd93045ebfa6ab07ce7017fb4095736c3f6f315a
tree415abc51803f927f02fd53b7811a61f040b5fcba
parentbce9a636beabbb2c538cdfca49592b04bfbf7e2c
target/riscv: rvv: Add mask agnostic for vector integer shift instructions

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165570784143.17634.35095816584573691-4@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn_trans/trans_rvv.c.inc
target/riscv/vector_helper.c