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(parent: 7df40c5) | patch
target/ppc: 7xx: Set SRRs directly in exception code
authorFabiano Rosas <farosas@linux.ibm.com>
Wed, 9 Feb 2022 08:08:56 +0000 (09:08 +0100)
committerCédric Le Goater <clg@kaod.org>
Wed, 9 Feb 2022 08:08:56 +0000 (09:08 +0100)
commitfe4b5c4c335c874ab05f3bdf40f2b62641d81c72
tree1ffcf328f87c1d80ae236dc5dff6d351946e1ebctree
parent7df40c5414b2f5e213fa30005f1600a429660cc5commit | diff
target/ppc: 7xx: Set SRRs directly in exception code

The 7xx CPUs don't have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-11-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
target/ppc/excp_helper.c diff | blob | blame | history
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