int interrupt_request;
int halted;
uint32_t mmu_bm;
int interrupt_request;
int halted;
uint32_t mmu_bm;
+ uint32_t mmu_ctpr_mask;
+ uint32_t mmu_cxr_mask;
+ uint32_t mmu_sfsr_mask;
+ uint32_t mmu_trcr_mask;
/* NOTE: we allow 8 more registers to handle wrapping */
target_ulong regbase[NWINDOWS * 16 + 8];
/* NOTE: we allow 8 more registers to handle wrapping */
target_ulong regbase[NWINDOWS * 16 + 8];
/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
/* Context base + context number */
/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
/* Context base + context number */
- pde_ptr = ((env->mmuregs[1] & ~63)<< 4) + (env->mmuregs[2] << 2);
+ pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
pde = ldl_phys(pde_ptr);
/* Ctx pde */
pde = ldl_phys(pde_ptr);
/* Ctx pde */
oldreg = env->mmuregs[reg];
switch(reg) {
oldreg = env->mmuregs[reg];
switch(reg) {
+ case 0: // Control Register
env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
(T1 & 0x00ffffff);
// Mappings generated during no-fault mode or MMU
env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
(T1 & 0x00ffffff);
// Mappings generated during no-fault mode or MMU
(env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm)))
tlb_flush(env, 1);
break;
(env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm)))
tlb_flush(env, 1);
break;
- case 2:
- env->mmuregs[reg] = T1;
+ case 1: // Context Table Pointer Register
+ env->mmuregs[reg] = T1 & env->mmu_ctpr_mask;
+ break;
+ case 2: // Context Register
+ env->mmuregs[reg] = T1 & env->mmu_cxr_mask;
if (oldreg != env->mmuregs[reg]) {
/* we flush when the MMU context changes because
QEMU has no MMU context support */
tlb_flush(env, 1);
}
break;
if (oldreg != env->mmuregs[reg]) {
/* we flush when the MMU context changes because
QEMU has no MMU context support */
tlb_flush(env, 1);
}
break;
+ case 3: // Synchronous Fault Status Register with Clear
+ case 4: // Synchronous Fault Address Register
+ break;
+ case 0x10: // TLB Replacement Control Register
+ env->mmuregs[reg] = T1 & env->mmu_trcr_mask;
- case 0x13:
- env->mmuregs[3] = T1;
+ case 0x13: // Synchronous Fault Status Register with Read and Clear
+ env->mmuregs[3] = T1 & env->mmu_sfsr_mask;
+ case 0x14: // Synchronous Fault Address Register
env->mmuregs[4] = T1;
break;
default:
env->mmuregs[4] = T1;
break;
default:
uint32_t fpu_version;
uint32_t mmu_version;
uint32_t mmu_bm;
uint32_t fpu_version;
uint32_t mmu_version;
uint32_t mmu_bm;
+ uint32_t mmu_ctpr_mask;
+ uint32_t mmu_cxr_mask;
+ uint32_t mmu_sfsr_mask;
+ uint32_t mmu_trcr_mask;
};
static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name);
};
static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name);
env->fsr = def->fpu_version;
#if !defined(TARGET_SPARC64)
env->mmu_bm = def->mmu_bm;
env->fsr = def->fpu_version;
#if !defined(TARGET_SPARC64)
env->mmu_bm = def->mmu_bm;
+ env->mmu_ctpr_mask = def->mmu_ctpr_mask;
+ env->mmu_cxr_mask = def->mmu_cxr_mask;
+ env->mmu_sfsr_mask = def->mmu_sfsr_mask;
+ env->mmu_trcr_mask = def->mmu_trcr_mask;
env->mmuregs[0] |= def->mmu_version;
cpu_sparc_set_id(env, 0);
#endif
env->mmuregs[0] |= def->mmu_version;
cpu_sparc_set_id(env, 0);
#endif
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
.mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
.mmu_bm = 0x00004000,
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
.mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "Fujitsu MB86904",
},
{
.name = "Fujitsu MB86904",
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
.mmu_bm = 0x00004000,
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x00ffffc0,
+ .mmu_cxr_mask = 0x000000ff,
+ .mmu_sfsr_mask = 0x00016fff,
+ .mmu_trcr_mask = 0x00ffffff,
},
{
.name = "Fujitsu MB86907",
},
{
.name = "Fujitsu MB86907",
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
.mmu_bm = 0x00004000,
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0xffffffc0,
+ .mmu_cxr_mask = 0x000000ff,
+ .mmu_sfsr_mask = 0x00016fff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "LSI L64811",
},
{
.name = "LSI L64811",
.fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
.mmu_version = 0x10 << 24,
.mmu_bm = 0x00004000,
.fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
.mmu_version = 0x10 << 24,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "Cypress CY7C601",
},
{
.name = "Cypress CY7C601",
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
.mmu_version = 0x10 << 24,
.mmu_bm = 0x00004000,
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
.mmu_version = 0x10 << 24,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "Cypress CY7C611",
},
{
.name = "Cypress CY7C611",
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
.mmu_version = 0x10 << 24,
.mmu_bm = 0x00004000,
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
.mmu_version = 0x10 << 24,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "TI SuperSparc II",
},
{
.name = "TI SuperSparc II",
.fpu_version = 0 << 17,
.mmu_version = 0x04000000,
.mmu_bm = 0x00002000,
.fpu_version = 0 << 17,
.mmu_version = 0x04000000,
.mmu_bm = 0x00002000,
+ .mmu_ctpr_mask = 0xffffffc0,
+ .mmu_cxr_mask = 0x0000ffff,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "TI MicroSparc I",
},
{
.name = "TI MicroSparc I",
.fpu_version = 4 << 17,
.mmu_version = 0x41000000,
.mmu_bm = 0x00004000,
.fpu_version = 4 << 17,
.mmu_version = 0x41000000,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0x00016fff,
+ .mmu_trcr_mask = 0x0000003f,
},
{
.name = "TI MicroSparc II",
},
{
.name = "TI MicroSparc II",
.fpu_version = 4 << 17,
.mmu_version = 0x02000000,
.mmu_bm = 0x00004000,
.fpu_version = 4 << 17,
.mmu_version = 0x02000000,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x00ffffc0,
+ .mmu_cxr_mask = 0x000000ff,
+ .mmu_sfsr_mask = 0x00016bff,
+ .mmu_trcr_mask = 0x00ffffff,
},
{
.name = "TI MicroSparc IIep",
},
{
.name = "TI MicroSparc IIep",
.fpu_version = 4 << 17,
.mmu_version = 0x04000000,
.mmu_bm = 0x00004000,
.fpu_version = 4 << 17,
.mmu_version = 0x04000000,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x00ffffc0,
+ .mmu_cxr_mask = 0x000000ff,
+ .mmu_sfsr_mask = 0x00016bff,
+ .mmu_trcr_mask = 0x00ffffff,
},
{
.name = "TI SuperSparc 51",
},
{
.name = "TI SuperSparc 51",
.fpu_version = 0 << 17,
.mmu_version = 0x04000000,
.mmu_bm = 0x00002000,
.fpu_version = 0 << 17,
.mmu_version = 0x04000000,
.mmu_bm = 0x00002000,
+ .mmu_ctpr_mask = 0xffffffc0,
+ .mmu_cxr_mask = 0x0000ffff,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "TI SuperSparc 61",
},
{
.name = "TI SuperSparc 61",
.fpu_version = 0 << 17,
.mmu_version = 0x04000000,
.mmu_bm = 0x00002000,
.fpu_version = 0 << 17,
.mmu_version = 0x04000000,
.mmu_bm = 0x00002000,
+ .mmu_ctpr_mask = 0xffffffc0,
+ .mmu_cxr_mask = 0x0000ffff,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "Ross RT625",
},
{
.name = "Ross RT625",
.fpu_version = 1 << 17,
.mmu_version = 0x1e000000,
.mmu_bm = 0x00004000,
.fpu_version = 1 << 17,
.mmu_version = 0x1e000000,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "Ross RT620",
},
{
.name = "Ross RT620",
.fpu_version = 1 << 17,
.mmu_version = 0x1f000000,
.mmu_bm = 0x00004000,
.fpu_version = 1 << 17,
.mmu_version = 0x1f000000,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "BIT B5010",
},
{
.name = "BIT B5010",
.fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
.mmu_version = 0x20000000,
.mmu_bm = 0x00004000,
.fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
.mmu_version = 0x20000000,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "Matsushita MN10501",
},
{
.name = "Matsushita MN10501",
.fpu_version = 0 << 17,
.mmu_version = 0x50000000,
.mmu_bm = 0x00004000,
.fpu_version = 0 << 17,
.mmu_version = 0x50000000,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "Weitek W8601",
},
{
.name = "Weitek W8601",
.fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
.mmu_version = 0x10 << 24,
.mmu_bm = 0x00004000,
.fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
.mmu_version = 0x10 << 24,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
.mmu_version = 0xf2000000,
.mmu_bm = 0x00004000,
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
.mmu_version = 0xf2000000,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
.mmu_version = 0xf3000000,
.mmu_bm = 0x00004000,
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
.mmu_version = 0xf3000000,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,