+static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ u32 dfx_val;
+
+ dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
+
+ if (dfx_val & BIT(16))
+ return false;
+
+ return true;
+}
+
+static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ int i, max_loop = 1000;
+ struct device *dev = &hisi_hba->pdev->dev;
+ u32 status, axi_status, dfx_val, dfx_tx_val;
+
+ for (i = 0; i < max_loop; i++) {
+ status = hisi_sas_read32_relaxed(hisi_hba,
+ AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
+
+ axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
+ dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
+ dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
+ phy_no, DMA_TX_FIFO_DFX0);
+
+ if ((status == 0x3) && (axi_status == 0x0) &&
+ (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
+ return true;
+ udelay(10);
+ }
+ dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
+ phy_no, status, axi_status,
+ dfx_val, dfx_tx_val);
+ return false;
+}
+
+static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ int i, max_loop = 1000;
+ struct device *dev = &hisi_hba->pdev->dev;
+ u32 status, tx_dfx0;
+
+ for (i = 0; i < max_loop; i++) {
+ status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
+ status = (status & 0x3fc0) >> 6;
+
+ if (status != 0x1)
+ return true;
+
+ tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
+ if ((tx_dfx0 & 0x1ff) == 0x2)
+ return true;
+ udelay(10);
+ }
+ dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
+ phy_no, status, tx_dfx0);
+ return false;
+}
+
+static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
+{
+ if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
+ return true;
+
+ if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
+ return false;
+
+ if (!wait_io_done_v2_hw(hisi_hba, phy_no))
+ return false;
+
+ return true;
+}
+
+