+ T0 &= ~(env->icache_line_size - 1);
+ tb_invalidate_page_range((uint64_t)T0,
+ (uint64_t)(T0 + env->icache_line_size));
+}
+#endif
+
+void glue(do_dcbz, MEMSUFFIX) (void)
+{
+ int dcache_line_size = env->dcache_line_size;
+
+ /* XXX: should be 970 specific (?) */
+ if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
+ dcache_line_size = 32;
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x00), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x04), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x08), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x0C), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x10), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x14), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x18), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x1C), 0);
+ if (dcache_line_size >= 64) {
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x20UL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x24UL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x28UL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x2CUL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x30UL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x34UL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x38UL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x3CUL), 0);
+ if (dcache_line_size >= 128) {
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x40UL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x44UL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x48UL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x4CUL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x50UL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x54UL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x58UL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x5CUL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x60UL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x64UL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x68UL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x6CUL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x70UL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x74UL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x78UL), 0);
+ glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x7CUL), 0);
+ }
+ }
+}
+
+#if defined(TARGET_PPC64)
+void glue(do_dcbz_64, MEMSUFFIX) (void)
+{
+ int dcache_line_size = env->dcache_line_size;
+
+ /* XXX: should be 970 specific (?) */
+ if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
+ dcache_line_size = 32;
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x00), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x04), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x08), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x0C), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x10), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x14), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x18), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x1C), 0);
+ if (dcache_line_size >= 64) {
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x20UL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x24UL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x28UL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x2CUL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x30UL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x34UL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x38UL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x3CUL), 0);
+ if (dcache_line_size >= 128) {
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x40UL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x44UL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x48UL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x4CUL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x50UL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x54UL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x58UL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x5CUL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x60UL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x64UL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x68UL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x6CUL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x70UL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x74UL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x78UL), 0);
+ glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x7CUL), 0);
+ }
+ }