The arch review of AIA spec is completed and we now have official
extension names for AIA: Smaia (M-mode AIA CSRs) and Ssaia (S-mode
AIA CSRs).
Refer, section 1.6 of the latest AIA v0.3.1 stable specification at
https://github.com/riscv/riscv-aia/releases/download/0.3.1-draft.32/riscv-interrupts-032.pdf)
Based on above, we update QEMU RISC-V to:
1) Have separate config options for Smaia and Ssaia extensions
which replace RISCV_FEATURE_AIA in CPU features
2) Not generate AIA INTC compatible string in virt machine
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
20220820042958.377018-1-apatel@ventanamicro.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
/* Force select AIA feature and setup CSR read-modify-write callback */
if (env) {
/* Force select AIA feature and setup CSR read-modify-write callback */
if (env) {
- riscv_set_feature(env, RISCV_FEATURE_AIA);
+ rcpu->cfg.ext_ssaia = true;
riscv_cpu_set_geilen(env, imsic->num_pages - 1);
riscv_cpu_set_geilen(env, imsic->num_pages - 1);
+ } else {
+ rcpu->cfg.ext_smaia = true;
}
riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S,
riscv_imsic_rmw, imsic);
}
riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S,
riscv_imsic_rmw, imsic);
qemu_fdt_add_subnode(mc->fdt, intc_name);
qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
intc_phandles[cpu]);
qemu_fdt_add_subnode(mc->fdt, intc_name);
qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
intc_phandles[cpu]);
- if (riscv_feature(&s->soc[socket].harts[cpu].env,
- RISCV_FEATURE_AIA)) {
- static const char * const compat[2] = {
- "riscv,cpu-intc-aia", "riscv,cpu-intc"
- };
- qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible",
- (char **)&compat, ARRAY_SIZE(compat));
- } else {
- qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
- "riscv,cpu-intc");
- }
+ qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
+ "riscv,cpu-intc");
qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
+ ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia),
+ ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia),
ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
- if (cpu->cfg.aia) {
- riscv_set_feature(env, RISCV_FEATURE_AIA);
- }
-
if (cpu->cfg.debug) {
riscv_set_feature(env, RISCV_FEATURE_DEBUG);
}
if (cpu->cfg.debug) {
riscv_set_feature(env, RISCV_FEATURE_DEBUG);
}
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
- DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
+ DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
+ DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false),
DEFINE_PROP_END_OF_LIST(),
};
DEFINE_PROP_END_OF_LIST(),
};
RISCV_FEATURE_PMP,
RISCV_FEATURE_EPMP,
RISCV_FEATURE_MISA,
RISCV_FEATURE_PMP,
RISCV_FEATURE_EPMP,
RISCV_FEATURE_MISA,
bool ext_zve32f;
bool ext_zve64f;
bool ext_zmmul;
bool ext_zve32f;
bool ext_zve64f;
bool ext_zmmul;
+ bool ext_smaia;
+ bool ext_ssaia;
bool rvv_ta_all_1s;
bool rvv_ma_all_1s;
bool rvv_ta_all_1s;
bool rvv_ma_all_1s;
bool mmu;
bool pmp;
bool epmp;
bool mmu;
bool pmp;
bool epmp;
bool debug;
uint64_t resetvec;
bool debug;
uint64_t resetvec;
int extirq, unsigned int extirq_def_prio,
uint64_t pending, uint8_t *iprio)
{
int extirq, unsigned int extirq_def_prio,
uint64_t pending, uint8_t *iprio)
{
+ RISCVCPU *cpu = env_archcpu(env);
int irq, best_irq = RISCV_EXCP_NONE;
unsigned int prio, best_prio = UINT_MAX;
int irq, best_irq = RISCV_EXCP_NONE;
unsigned int prio, best_prio = UINT_MAX;
- if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+ if (!((extirq == IRQ_M_EXT) ? cpu->cfg.ext_smaia : cpu->cfg.ext_ssaia)) {
static int aia_any(CPURISCVState *env, int csrno)
{
static int aia_any(CPURISCVState *env, int csrno)
{
- if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+ RISCVCPU *cpu = env_archcpu(env);
+
+ if (!cpu->cfg.ext_smaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
return RISCV_EXCP_ILLEGAL_INST;
}
static int aia_any32(CPURISCVState *env, int csrno)
{
static int aia_any32(CPURISCVState *env, int csrno)
{
- if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+ RISCVCPU *cpu = env_archcpu(env);
+
+ if (!cpu->cfg.ext_smaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
return RISCV_EXCP_ILLEGAL_INST;
}
static int aia_smode(CPURISCVState *env, int csrno)
{
static int aia_smode(CPURISCVState *env, int csrno)
{
- if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+ RISCVCPU *cpu = env_archcpu(env);
+
+ if (!cpu->cfg.ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
return RISCV_EXCP_ILLEGAL_INST;
}
static int aia_smode32(CPURISCVState *env, int csrno)
{
static int aia_smode32(CPURISCVState *env, int csrno)
{
- if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+ RISCVCPU *cpu = env_archcpu(env);
+
+ if (!cpu->cfg.ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
return RISCV_EXCP_ILLEGAL_INST;
}
static int aia_hmode(CPURISCVState *env, int csrno)
{
static int aia_hmode(CPURISCVState *env, int csrno)
{
- if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+ RISCVCPU *cpu = env_archcpu(env);
+
+ if (!cpu->cfg.ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
return RISCV_EXCP_ILLEGAL_INST;
}
static int aia_hmode32(CPURISCVState *env, int csrno)
{
static int aia_hmode32(CPURISCVState *env, int csrno)
{
- if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+ RISCVCPU *cpu = env_archcpu(env);
+
+ if (!cpu->cfg.ext_ssaia) {
return RISCV_EXCP_ILLEGAL_INST;
}
return RISCV_EXCP_ILLEGAL_INST;
}