}
}
+static void dpp3_power_on_hdr3dlut(
+ struct dpp *dpp_base,
+ bool power_on)
+{
+ struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
+
+ if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
+ REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, power_on ? 0 : 3);
+ if (power_on)
+ REG_WAIT(CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, 0, 1, 5);
+ }
+}
+
+static void dpp3_power_on_shaper(
+ struct dpp *dpp_base,
+ bool power_on)
+{
+ struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
+
+ if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) {
+ REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, power_on ? 0 : 3);
+ if (power_on)
+ REG_WAIT(CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, 0, 1, 5);
+ }
+}
+
static void dpp3_configure_blnd_lut(
struct dpp *dpp_base,
bool is_ram_a)
if (params == NULL) {
REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0);
+ if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
+ dpp3_power_on_shaper(dpp_base, false);
return false;
}
+
+ if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
+ dpp3_power_on_shaper(dpp_base, true);
+
current_mode = dpp3_get_shaper_current(dpp_base);
if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
if (params == NULL) {
dpp3_set_3dlut_mode(dpp_base, LUT_BYPASS, false, false);
+ if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
+ dpp3_power_on_hdr3dlut(dpp_base, false);
return false;
}
+
+ if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm)
+ dpp3_power_on_hdr3dlut(dpp_base, true);
+
mode = get3dlut_config(dpp_base, &is_17x17x17, &is_12bits_color_channel);
if (mode == LUT_BYPASS || mode == LUT_RAM_B)
TF_REG_LIST_DCN20_COMMON(id), \
SRI(CM_BLNDGAM_CONTROL, CM, id), \
SRI(CM_SHAPER_LUT_DATA, CM, id),\
+ SRI(CM_MEM_PWR_CTRL2, CM, id), \
+ SRI(CM_MEM_PWR_STATUS2, CM, id), \
SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, CM, id),\
SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, CM, id),\
SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, CM, id),\
#define DPP_REG_LIST_SH_MASK_DCN30_UPDATED(mask_sh)\
TF_SF(CM0_CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, mask_sh), \
+ TF_SF(CM0_CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, mask_sh),\
+ TF_SF(CM0_CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, mask_sh),\
+ TF_SF(CM0_CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, mask_sh),\
+ TF_SF(CM0_CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, mask_sh),\
TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, mask_sh), \
TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, mask_sh), \
type CM_BIAS_CR_R;\
type GAMCOR_MEM_PWR_DIS; \
type GAMCOR_MEM_PWR_FORCE; \
+ type HDR3DLUT_MEM_PWR_FORCE; \
+ type SHAPER_MEM_PWR_FORCE; \
type PRE_DEGAM_MODE;\
type PRE_DEGAM_SELECT;\
type CNVC_ALPHA_PLANE_ENABLE; \
type CM_BLNDGAM_SELECT_CURRENT; \
type CM_BLNDGAM_SELECT; \
type GAMCOR_MEM_PWR_STATE; \
- type BLNDGAM_MEM_PWR_STATE
+ type BLNDGAM_MEM_PWR_STATE; \
+ type HDR3DLUT_MEM_PWR_STATE; \
+ type SHAPER_MEM_PWR_STATE
struct dcn3_dpp_shift {
DPP_REG_FIELD_LIST_DCN3(uint8_t);
#define DPP_DCN3_REG_VARIABLE_LIST_COMMON \
DPP_DCN2_REG_VARIABLE_LIST; \
uint32_t CM_MEM_PWR_STATUS;\
+ uint32_t CM_MEM_PWR_STATUS2;\
+ uint32_t CM_MEM_PWR_CTRL2;\
uint32_t CM_DEALPHA;\
uint32_t CM_BIAS_CR_R;\
uint32_t CM_BIAS_Y_G_CB_B;\