target-tricore: fix RRPW_DEXTR using wrong reg

RRPW_DEXTR used r1 for the low part and r2 for the high part. It should be the
other way round. This also fixes that the result of the first shift was not
saved in a temp and could overwrite registers that were needed for the second
shift.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 989a047991e6a01ff5bd23b947426c4ccfd46e67..bbcfee9754f21f954a0ee280de7d44650e96f07d 100644 (file)
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -8044,8 +8044,8 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
             tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16);
         } else {
             temp = tcg_temp_new();
-            tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], const16);
-            tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 32 - const16);
+            tcg_gen_shli_tl(temp, cpu_gpr_d[r1], const16);
+            tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], 32 - const16);
             tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
             tcg_temp_free(temp);
         }