int cpu_inl(CPUState *env, int addr);
#endif
+/* address in the RAM (different from a physical address) */
+#ifdef USE_KQEMU
+typedef uint32_t ram_addr_t;
+#else
+typedef unsigned long ram_addr_t;
+#endif
+
/* memory API */
-extern int phys_ram_size;
+extern ram_addr_t phys_ram_size;
extern int phys_ram_fd;
extern uint8_t *phys_ram_base;
extern uint8_t *phys_ram_dirty;
+extern ram_addr_t ram_size;
/* physical memory access */
#define TLB_INVALID_MASK (1 << 3)
typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
void cpu_register_physical_memory(target_phys_addr_t start_addr,
- unsigned long size,
- unsigned long phys_offset);
-uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr);
-ram_addr_t qemu_ram_alloc(unsigned int size);
+ ram_addr_t size,
+ ram_addr_t phys_offset);
+ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
+ram_addr_t qemu_ram_alloc(ram_addr_t);
void qemu_ram_free(ram_addr_t addr);
int cpu_register_io_memory(int io_index,
CPUReadMemoryFunc **mem_read,
#error TARGET_PHYS_ADDR_BITS undefined
#endif
-/* address in the RAM (different from a physical address) */
-typedef unsigned long ram_addr_t;
-
#define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
#define EXCP_INTERRUPT 0x10000 /* async interruption */
void cpu_resume_from_signal(CPUState *env1, void *puc);
void cpu_exec_init(CPUState *env);
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
-void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
+void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, target_ulong addr);
#define TARGET_VIRT_ADDR_SPACE_BITS 42
#elif defined(TARGET_PPC64)
#define TARGET_PHYS_ADDR_SPACE_BITS 42
+#elif defined(TARGET_X86_64) && !defined(USE_KQEMU)
+#define TARGET_PHYS_ADDR_SPACE_BITS 42
+#elif defined(TARGET_I386) && !defined(USE_KQEMU)
+#define TARGET_PHYS_ADDR_SPACE_BITS 36
#else
/* Note: for compatibility with kqemu, we use 32 bits for x86_64 */
#define TARGET_PHYS_ADDR_SPACE_BITS 32
uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE] __attribute__((aligned (32)));
uint8_t *code_gen_ptr;
-int phys_ram_size;
+ram_addr_t phys_ram_size;
int phys_ram_fd;
uint8_t *phys_ram_base;
uint8_t *phys_ram_dirty;
typedef struct PhysPageDesc {
/* offset in host memory of the page + io_index in the low 12 bits */
- uint32_t phys_offset;
+ ram_addr_t phys_offset;
} PhysPageDesc;
#define L2_BITS 10
#endif
}
-static inline PageDesc *page_find_alloc(unsigned int index)
+static inline PageDesc *page_find_alloc(target_ulong index)
{
PageDesc **lp, *p;
return p + (index & (L2_SIZE - 1));
}
-static inline PageDesc *page_find(unsigned int index)
+static inline PageDesc *page_find(target_ulong index)
{
PageDesc *p;
tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
}
-static inline void tb_phys_invalidate(TranslationBlock *tb, unsigned int page_addr)
+static inline void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr)
{
CPUState *env;
PageDesc *p;
unsigned int h, n1;
- target_ulong phys_pc;
+ target_phys_addr_t phys_pc;
TranslationBlock *tb1, *tb2;
/* remove the TB from the hash list */
the same physical page. 'is_cpu_write_access' should be true if called
from a real cpu write access: the virtual CPU will exit the current
TB if code is modified inside this TB. */
-void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
+void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
int is_cpu_write_access)
{
int n, current_tb_modified, current_tb_not_found, current_flags;
}
/* len must be <= 8 and start must be a multiple of len */
-static inline void tb_invalidate_phys_page_fast(target_ulong start, int len)
+static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
{
PageDesc *p;
int offset, b;
}
#if !defined(CONFIG_SOFTMMU)
-static void tb_invalidate_phys_page(target_ulong addr,
+static void tb_invalidate_phys_page(target_phys_addr_t addr,
unsigned long pc, void *puc)
{
int n, current_flags, current_tb_modified;
#endif /* defined(CONFIG_USER_ONLY) */
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
- int memory);
-static void *subpage_init (target_phys_addr_t base, uint32_t *phys,
- int orig_memory);
+ ram_addr_t memory);
+static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
+ ram_addr_t orig_memory);
#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
need_subpage) \
do { \
page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
io memory page */
void cpu_register_physical_memory(target_phys_addr_t start_addr,
- unsigned long size,
- unsigned long phys_offset)
+ ram_addr_t size,
+ ram_addr_t phys_offset)
{
target_phys_addr_t addr, end_addr;
PhysPageDesc *p;
CPUState *env;
- unsigned long orig_size = size;
+ ram_addr_t orig_size = size;
void *subpage;
size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
p = phys_page_find(addr >> TARGET_PAGE_BITS);
if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
- unsigned long orig_memory = p->phys_offset;
+ ram_addr_t orig_memory = p->phys_offset;
target_phys_addr_t start_addr2, end_addr2;
int need_subpage = 0;
}
/* XXX: temporary until new memory mapping API */
-uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr)
+ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
{
PhysPageDesc *p;
}
/* XXX: better than nothing */
-ram_addr_t qemu_ram_alloc(unsigned int size)
+ram_addr_t qemu_ram_alloc(ram_addr_t size)
{
ram_addr_t addr;
if ((phys_ram_alloc_offset + size) > phys_ram_size) {
- fprintf(stderr, "Not enough memory (requested_size = %u, max memory = %d)\n",
+ fprintf(stderr, "Not enough memory (requested_size = %lu, max memory = %ld)\n",
size, phys_ram_size);
abort();
}
};
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
- int memory)
+ ram_addr_t memory)
{
int idx, eidx;
unsigned int i;
return 0;
}
-static void *subpage_init (target_phys_addr_t base, uint32_t *phys,
- int orig_memory)
+static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
+ ram_addr_t orig_memory)
{
subpage_t *mmio;
int subpage_memory;
/* Board init. */
-static void an5206_init(int ram_size, int vga_ram_size,
+static void an5206_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
#ifndef HW_BOARDS_H
#define HW_BOARDS_H
-typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
+typedef void QEMUMachineInitFunc(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,
/* Board init. */
-static void dummy_m68k_init(int ram_size, int vga_ram_size,
+static void dummy_m68k_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
void etraxfs_ser_init(CPUState *env, qemu_irq *irqs, target_phys_addr_t base);
static
-void bareetraxfs_init (int ram_size, int vga_ram_size,
+void bareetraxfs_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
static const int sector_len = 128 * 1024;
-static void connex_init(int ram_size, int vga_ram_size,
+static void connex_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
pxa2xx_gpio_in_get(cpu->gpio)[36]);
}
-static void verdex_init(int ram_size, int vga_ram_size,
+static void verdex_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
.board_id = 0x113,
};
-static void integratorcp_init(int ram_size, int vga_ram_size,
+static void integratorcp_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
.ram_size = 0x04000000,
};
-static void mainstone_common_init(int ram_size, int vga_ram_size,
+static void mainstone_common_init(ram_addr_t ram_size, int vga_ram_size,
DisplayState *ds, const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, enum mainstone_model_e model, int arm_id)
arm_load_kernel(cpu->env, &mainstone_binfo);
}
-static void mainstone_init(int ram_size, int vga_ram_size,
+static void mainstone_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
}
}
-static void mcf5208evb_init(int ram_size, int vga_ram_size,
+static void mcf5208evb_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
static
-void mips_jazz_init (int ram_size, int vga_ram_size,
+void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
DisplayState *ds, const char *cpu_model,
enum jazz_model_e jazz_model)
{
}
static
-void mips_magnum_init (int ram_size, int vga_ram_size,
+void mips_magnum_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
}
static
-void mips_pica61_init (int ram_size, int vga_ram_size,
+void mips_pica61_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
}
static
-void mips_malta_init (int ram_size, int vga_ram_size,
+void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
}
static void
-mips_mipssim_init (int ram_size, int vga_ram_size,
+mips_mipssim_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
static const int sector_len = 32 * 1024;
static
-void mips_r4k_init (int ram_size, int vga_ram_size,
+void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
.atag_board = n800_atag_setup,
};
-static void n800_init(int ram_size, int vga_ram_size,
+static void n800_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
.board_id = 0x331,
};
-static void palmte_init(int ram_size, int vga_ram_size,
+static void palmte_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
}
/* hd_table must contain 4 block drivers */
-static void cmos_init(int ram_size, const char *boot_device, BlockDriverState **hd_table)
+static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
+ const char *boot_device, BlockDriverState **hd_table)
{
RTCState *s = rtc_state;
int nbds, bds[3] = { 0, };
rtc_set_memory(s, 0x30, val);
rtc_set_memory(s, 0x31, val >> 8);
+ if (above_4g_mem_size) {
+ rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
+ rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
+ rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
+ }
+
if (ram_size > (16 * 1024 * 1024))
val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
else
}
/* PC hardware initialisation */
-static void pc_init1(int ram_size, int vga_ram_size,
+static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename,
char buf[1024];
int ret, linux_boot, i;
ram_addr_t ram_addr, vga_ram_addr, bios_offset, vga_bios_offset;
+ ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
int bios_size, isa_bios_size, vga_bios_size;
PCIBus *pci_bus;
int piix3_devfn = -1;
BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
BlockDriverState *fd[MAX_FD];
+ if (ram_size >= 0xe0000000 ) {
+ above_4g_mem_size = ram_size - 0xe0000000;
+ below_4g_mem_size = 0xe0000000;
+ } else {
+ below_4g_mem_size = ram_size;
+ }
+
linux_boot = (kernel_filename != NULL);
/* init CPUs */
/* allocate RAM */
ram_addr = qemu_ram_alloc(ram_size);
- cpu_register_physical_memory(0, ram_size, ram_addr);
+ cpu_register_physical_memory(0, below_4g_mem_size, ram_addr);
+
+ /* above 4giga memory allocation */
+ if (above_4g_mem_size > 0) {
+ cpu_register_physical_memory(0x100000000ULL, above_4g_mem_size,
+ ram_addr + below_4g_mem_size);
+ }
/* allocate VGA RAM */
vga_ram_addr = qemu_ram_alloc(vga_ram_size);
}
floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
- cmos_init(ram_size, boot_device, hd);
+ cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
if (pci_enabled && usb_enabled) {
usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
}
}
-static void pc_init_pci(int ram_size, int vga_ram_size,
+static void pc_init_pci(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,
initrd_filename, 1, cpu_model);
}
-static void pc_init_isa(int ram_size, int vga_ram_size,
+static void pc_init_isa(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,
return (irq_num + slot_addend) & 3;
}
-static uint32_t isa_page_descs[384 / 4];
+static target_phys_addr_t isa_page_descs[384 / 4];
static uint8_t smm_enabled;
static int pci_irq_levels[4];
}
}
-static void ref405ep_init (int ram_size, int vga_ram_size,
+static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,
}
}
-static void taihu_405ep_init(int ram_size, int vga_ram_size,
+static void taihu_405ep_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,
};
/* PowerPC Mac99 hardware initialisation */
-static void ppc_core99_init (int ram_size, int vga_ram_size,
+static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,
return 1; /* osi_call handled */
}
-static void ppc_heathrow_init (int ram_size, int vga_ram_size,
+static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,
#define NVRAM_SIZE 0x2000
/* PowerPC PREP hardware initialisation */
-static void ppc_prep_init (int ram_size, int vga_ram_size,
+static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename,
const char *kernel_cmdline,
#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
#define SDRAM_SIZE 0x04000000
-static void r2d_init(int ram_size, int vga_ram_size,
+static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState * ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
.board_id = 0x33b,
};
-static void realview_init(int ram_size, int vga_ram_size,
+static void realview_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
/* XXXXX */
}
-static void shix_init(int ram_size, int vga_ram_size,
+static void shix_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState * ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
.ram_size = 0x04000000,
};
-static void spitz_common_init(int ram_size, int vga_ram_size,
+static void spitz_common_init(ram_addr_t ram_size, int vga_ram_size,
DisplayState *ds, const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, enum spitz_model_e model, int arm_id)
sl_bootparam_write(SL_PXA_PARAM_BASE - PXA2XX_SDRAM_BASE);
}
-static void spitz_init(int ram_size, int vga_ram_size,
+static void spitz_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
}
-static void borzoi_init(int ram_size, int vga_ram_size,
+static void borzoi_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
}
-static void akita_init(int ram_size, int vga_ram_size,
+static void akita_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
}
-static void terrier_init(int ram_size, int vga_ram_size,
+static void terrier_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
}
/* FIXME: Figure out how to generate these from stellaris_boards. */
-static void lm3s811evb_init(int ram_size, int vga_ram_size,
+static void lm3s811evb_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
stellaris_init(kernel_filename, cpu_model, ds, &stellaris_boards[0]);
}
-static void lm3s6965evb_init(int ram_size, int vga_ram_size,
+static void lm3s6965evb_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
};
/* SPARCstation 5 hardware initialisation */
-static void ss5_init(int RAM_size, int vga_ram_size,
+static void ss5_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
}
/* SPARCstation 10 hardware initialisation */
-static void ss10_init(int RAM_size, int vga_ram_size,
+static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
}
/* SPARCserver 600MP hardware initialisation */
-static void ss600mp_init(int RAM_size, int vga_ram_size,
+static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
}
/* SPARCstation 20 hardware initialisation */
-static void ss20_init(int RAM_size, int vga_ram_size,
+static void ss20_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
}
/* SPARCstation 2 hardware initialisation */
-static void ss2_init(int RAM_size, int vga_ram_size,
+static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
}
/* SPARCserver 1000 hardware initialisation */
-static void ss1000_init(int RAM_size, int vga_ram_size,
+static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
}
/* SPARCcenter 2000 hardware initialisation */
-static void ss2000_init(int RAM_size, int vga_ram_size,
+static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
static fdctrl_t *floppy_controller;
/* Sun4u hardware initialisation */
-static void sun4u_init(int ram_size, int vga_ram_size,
+static void sun4u_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_devices, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
static struct arm_boot_info versatile_binfo;
-static void versatile_init(int ram_size, int vga_ram_size,
+static void versatile_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model,
arm_load_kernel(env, &versatile_binfo);
}
-static void vpb_init(int ram_size, int vga_ram_size,
+static void vpb_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
initrd_filename, cpu_model, 0x183);
}
-static void vab_init(int ram_size, int vga_ram_size,
+static void vab_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
int64_t free_space;
int ram_mb;
- extern int ram_size;
free_space = (int64_t)stfs.f_bavail * stfs.f_bsize;
if ((ram_size + 8192 * 1024) >= free_space) {
ram_mb = (ram_size / (1024 * 1024));
be needed to boot from old floppy disks.
@item -m @var{megs}
-Set virtual RAM size to @var{megs} megabytes. Default is 128 MiB.
+Set virtual RAM size to @var{megs} megabytes. Default is 128 MiB. Optionally,
+a suffix of ``M'' or ``G'' can be used to signify a value in megabytes or
+gigabytes respectively.
@item -smp @var{n}
Simulate an SMP system with @var{n} CPUs. On the PC target, up to 255
/* SLIRP */
void do_info_slirp(void);
-extern int ram_size;
extern int bios_size;
extern int cirrus_vga_enabled;
extern int vmsvga_enabled;
break;
case 0x80000008:
/* virtual & phys address size in low 2 bytes. */
- EAX = 0x00003028;
+/* XXX: This value must match the one used in the MMU code. */
+#if defined(TARGET_X86_64)
+# if defined(USE_KQEMU)
+ EAX = 0x00003020; /* 48 bits virtual, 32 bits physical */
+# else
+/* XXX: The physical address space is limited to 42 bits in exec.c. */
+ EAX = 0x00003028; /* 48 bits virtual, 40 bits physical */
+# endif
+#else
+# if defined(USE_KQEMU)
+ EAX = 0x00000020; /* 32 bits physical */
+# else
+ EAX = 0x00000024; /* 36 bits physical */
+# endif
+#endif
EBX = 0;
ECX = 0;
EDX = 0;
#else
-/* Bits 52-62 of a PTE are reserved. Bit 63 is the NX bit. */
-#define PHYS_ADDR_MASK 0xffffffffff000L
+/* XXX: This value should match the one returned by CPUID
+ * and in exec.c */
+#if defined(USE_KQEMU)
+#define PHYS_ADDR_MASK 0xfffff000L
+#else
+# if defined(TARGET_X86_64)
+# define PHYS_ADDR_MASK 0xfffffff000L
+# else
+# define PHYS_ADDR_MASK 0xffffff000L
+# endif
+#endif
/* return value:
-1 = cannot handle fault
//#define DEBUG_UNUSED_IOPORT
//#define DEBUG_IOPORT
-#define PHYS_RAM_MAX_SIZE (2047 * 1024 * 1024)
-
#ifdef TARGET_PPC
#define DEFAULT_RAM_SIZE 144
#else
int curses;
const char* keyboard_layout = NULL;
int64_t ticks_per_sec;
-int ram_size;
+ram_addr_t ram_size;
int pit_min_timer_count = 0;
int nb_nics;
NICInfo nd_table[MAX_NICS];
static int ram_load_v1(QEMUFile *f, void *opaque)
{
- int i, ret;
+ int ret;
+ ram_addr_t i;
if (qemu_get_be32(f) != phys_ram_size)
return -EINVAL;
static void ram_save(QEMUFile *f, void *opaque)
{
- int i;
+ ram_addr_t i;
RamCompressState s1, *s = &s1;
uint8_t buf[10];
{
RamDecompressState s1, *s = &s1;
uint8_t buf[10];
- int i;
+ ram_addr_t i;
if (version_id == 1)
return ram_load_v1(f, opaque);
}
if (buf[0] == 0) {
if (ram_decompress_buf(s, phys_ram_base + i, BDRV_HASH_BLOCK_SIZE) < 0) {
- fprintf(stderr, "Error while reading ram block address=0x%08x", i);
+ fprintf(stderr, "Error while reading ram block address=0x%08" PRIx64, (uint64_t)i);
goto error;
}
} else
case QEMU_OPTION_h:
help(0);
break;
- case QEMU_OPTION_m:
- ram_size = atoi(optarg) * 1024 * 1024;
- if (ram_size <= 0)
- help(1);
- if (ram_size > PHYS_RAM_MAX_SIZE) {
- fprintf(stderr, "qemu: at most %d MB RAM can be simulated\n",
- PHYS_RAM_MAX_SIZE / (1024 * 1024));
+ case QEMU_OPTION_m: {
+ uint64_t value;
+ char *ptr;
+
+ value = strtoul(optarg, &ptr, 10);
+ switch (*ptr) {
+ case 0: case 'M': case 'm':
+ value <<= 20;
+ break;
+ case 'G': case 'g':
+ value <<= 30;
+ break;
+ default:
+ fprintf(stderr, "qemu: invalid ram size: %s\n", optarg);
exit(1);
}
+
+ /* On 32-bit hosts, QEMU is limited by virtual address space */
+ if (value > (2047 << 20)
+#ifndef USE_KQEMU
+ && HOST_LONG_BITS == 32
+#endif
+ ) {
+ fprintf(stderr, "qemu: at most 2047 MB RAM can be simulated\n");
+ exit(1);
+ }
+ if (value != (uint64_t)(ram_addr_t)value) {
+ fprintf(stderr, "qemu: ram size too large\n");
+ exit(1);
+ }
+ ram_size = value;
break;
+ }
case QEMU_OPTION_d:
{
int mask;