MIPS: smp-cps: duplicate core0 CCA on secondary cores

Rather than hardcoding CCA=0x5 for secondary cores, re-use the CCA from
the boot CPU. This allows overrides of the CCA using the cca= kernel
parameter to take effect on all CPUs for consistency.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 1c865ae922a511e12022c705f73a1a75cc878c0a..6f4f739dad9635521eb0c8697365a3efd69f28eb 100644 (file)
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -45,10 +45,12 @@
 
 LEAF(mips_cps_core_entry)
        /*
-        * These first 8 bytes will be patched by cps_smp_setup to load the
-        * base address of the CM GCRs into register v1.
+        * These first 12 bytes will be patched by cps_smp_setup to load the
+        * base address of the CM GCRs into register v1 and the CCA to use into
+        * register s0.
         */
        .quad   0
+       .word   0
 
        /* Check whether we're here due to an NMI */
        mfc0    k0, CP0_STATUS
@@ -139,10 +141,11 @@ icache_done:
         add    a0, a0, t0
 dcache_done:
 
-       /* Set Kseg0 cacheable, coherent, write-back, write-allocate */
+       /* Set Kseg0 CCA to that in s0 */
        mfc0    t0, CP0_CONFIG
        ori     t0, 0x7
-       xori    t0, 0x2
+       xori    t0, 0x7
+       or      t0, t0, s0
        mtc0    t0, CP0_CONFIG
        ehb
 

diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index 6b96fedf0407d675428e7ca742dadc5500a95090..9e21bdd47043ad67fa44dc48a4383774dd01bb37 100644 (file)
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -123,9 +123,15 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
                }
        }
 
-       /* Patch the start of mips_cps_core_entry to provide the CM base */
+       /*
+        * Patch the start of mips_cps_core_entry to provide:
+        *
+        * v0 = CM base address
+        * s0 = kseg0 CCA
+        */
        entry_code = (u32 *)&mips_cps_core_entry;
        UASM_i_LA(&entry_code, 3, (long)mips_cm_base);
+       uasm_i_addiu(&entry_code, 16, 0, cca);
        dma_cache_wback_inv((unsigned long)&mips_cps_core_entry,
                            (void *)entry_code - (void *)&mips_cps_core_entry);