drm/msm: Remove dpu_encoder_phys_ops->hw_reset()

We call out of the virt encoder into phys only to call back into the
virt for hw reset. So remove the indirection and just call the virt
function directly.

Reviewed-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 96cdf06e7da21d8f5bf576014f149f2efbbc7298..bb69a5c9b471bfcf21bfe61606cf321526ac84cf 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1507,7 +1507,7 @@ static int dpu_encoder_helper_wait_event_timeout(
        return rc;
 }
 
-void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
+static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
 {
        struct dpu_encoder_virt *dpu_enc;
        struct dpu_hw_ctl *ctl;
@@ -1803,9 +1803,7 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
        if (needs_hw_reset) {
                trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
                for (i = 0; i < dpu_enc->num_phys_encs; i++) {
-                       phys = dpu_enc->phys_encs[i];
-                       if (phys && phys->ops.hw_reset)
-                               phys->ops.hw_reset(phys);
+                       dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
                }
        }
 }

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 964efcc757a4dcb53b9cae05e688ae9745f9089d..3a67bb9f9d9d9908c53c85ebf8f99858c8b716eb 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -114,8 +114,6 @@ struct dpu_encoder_virt_ops {
  * @handle_post_kickoff:       Do any work necessary post-kickoff work
  * @trigger_start:             Process start event on physical encoder
  * @needs_single_flush:                Whether encoder slaves need to be flushed
- * @hw_reset:                  Issue HW recovery such as CTL reset and clear
- *                             DPU_ENC_ERR_NEEDS_HW_RESET state
  * @irq_control:               Handler to enable/disable all the encoder IRQs
  * @prepare_idle_pc:           phys encoder can update the vsync_enable status
  *                              on idle power collapse prepare
@@ -151,7 +149,6 @@ struct dpu_encoder_phys_ops {
        void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
        void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
        bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
-       void (*hw_reset)(struct dpu_encoder_phys *phys_enc);
        void (*irq_control)(struct dpu_encoder_phys *phys, bool enable);
        void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
        void (*restore)(struct dpu_encoder_phys *phys);
@@ -342,15 +339,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
  */
 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc);
 
-/**
- * dpu_encoder_helper_hw_reset - issue ctl hw reset
- *     This helper function may be optionally specified by physical
- *     encoders if they require ctl hw reset. If state is currently
- *     DPU_ENC_ERR_NEEDS_HW_RESET, it is set back to DPU_ENC_ENABLED.
- * @phys_enc: Pointer to physical encoder structure
- */
-void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc);
-
 static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
                struct dpu_encoder_phys *phys_enc)
 {

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index b2d7f0ded24c051247869eeebb71f36615524083..c30ae05b33490345d4295dd6bb01e9860fbd1a0d 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -776,7 +776,6 @@ static void dpu_encoder_phys_cmd_init_ops(
        ops->wait_for_vblank = dpu_encoder_phys_cmd_wait_for_vblank;
        ops->trigger_start = dpu_encoder_phys_cmd_trigger_start;
        ops->needs_single_flush = dpu_encoder_phys_cmd_needs_single_flush;
-       ops->hw_reset = dpu_encoder_helper_hw_reset;
        ops->irq_control = dpu_encoder_phys_cmd_irq_control;
        ops->restore = dpu_encoder_phys_cmd_enable_helper;
        ops->prepare_idle_pc = dpu_encoder_phys_cmd_prepare_idle_pc;

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 84de385a9f6223881433bec56a38674598fb9d42..283a2491f3e36ca74387443ac1377fcea53b4043 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -766,7 +766,6 @@ static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)
        ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;
        ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;
        ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush;
-       ops->hw_reset = dpu_encoder_helper_hw_reset;
        ops->get_line_count = dpu_encoder_phys_vid_get_line_count;
 }