]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/commitdiff
Revert "bcm2835-i2s: setup clock only if CPU is clock master"
authorMartin Sperl <kernel@martin.sperl.org>
Wed, 31 Aug 2016 11:52:05 +0000 (11:52 +0000)
committerThadeu Lima de Souza Cascardo <cascardo@canonical.com>
Fri, 3 Feb 2017 15:42:45 +0000 (13:42 -0200)
This reverts commit fb8d849c7ee266ea557e54751275fe4d214596a0.

sound/soc/bcm/bcm2835-i2s.c

index d5e412302811ed8b007fc53f0aa2b5ddd12774b6..0f35d7c0f4026bb50a7223461b907b9797bd9a05 100644 (file)
@@ -411,25 +411,15 @@ static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
                divf = dividend & BCM2835_CLK_DIVF_MASK;
        }
 
-       /* Clock should only be set up here if CPU is clock master */
-       switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
-       case SND_SOC_DAIFMT_CBS_CFS:
-       case SND_SOC_DAIFMT_CBS_CFM:
-               /* Set clock divider */
-               regmap_write(dev->clk_regmap, BCM2835_CLK_PCMDIV_REG,
-                                 BCM2835_CLK_PASSWD
-                               | BCM2835_CLK_DIVI(divi)
-                               | BCM2835_CLK_DIVF(divf));
-
-               /* Setup clock, but don't start it yet */
-               regmap_write(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG,
-                                 BCM2835_CLK_PASSWD
-                               | BCM2835_CLK_MASH(mash)
-                               | BCM2835_CLK_SRC(clk_src));
-               break;
-       default:
-               break;
-       }
+       /* Set clock divider */
+       regmap_write(dev->clk_regmap, BCM2835_CLK_PCMDIV_REG, BCM2835_CLK_PASSWD
+                       | BCM2835_CLK_DIVI(divi)
+                       | BCM2835_CLK_DIVF(divf));
+
+       /* Setup clock, but don't start it yet */
+       regmap_write(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG, BCM2835_CLK_PASSWD
+                       | BCM2835_CLK_MASH(mash)
+                       | BCM2835_CLK_SRC(clk_src));
 
        /* Setup the frame format */
        format = BCM2835_I2S_CHEN;