arm64: dts: ti: k3-j7200: Add I2C nodes

J7200 has 7 I2Cs in main domain, 2 I2Cs in MCU and 1 in wakeup domain.
Add DT nodes for the same.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Faiz Abbas <faiz_abbas@ti.com>
Link: https://lore.kernel.org/r/20200923155400.13757-2-vigneshr@ti.com

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index c2a986affb0e753c708dd520e0cea1a98b8de724..a65ca56fbc59a1108a19ba80d35878a871a65c94 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -281,4 +281,81 @@
                clocks = <&k3_clks 286 2>;
                clock-names = "fclk";
        };
+
+       main_i2c0: i2c@2000000 {
+               compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+               reg = <0x00 0x2000000 0x00 0x100>;
+               interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "fck";
+               clocks = <&k3_clks 187 1>;
+               power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
+       };
+
+       main_i2c1: i2c@2010000 {
+               compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+               reg = <0x00 0x2010000 0x00 0x100>;
+               interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "fck";
+               clocks = <&k3_clks 188 1>;
+               power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
+       };
+
+       main_i2c2: i2c@2020000 {
+               compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+               reg = <0x00 0x2020000 0x00 0x100>;
+               interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "fck";
+               clocks = <&k3_clks 189 1>;
+               power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
+       };
+
+       main_i2c3: i2c@2030000 {
+               compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+               reg = <0x00 0x2030000 0x00 0x100>;
+               interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "fck";
+               clocks = <&k3_clks 190 1>;
+               power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
+       };
+
+       main_i2c4: i2c@2040000 {
+               compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+               reg = <0x00 0x2040000 0x00 0x100>;
+               interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "fck";
+               clocks = <&k3_clks 191 1>;
+               power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
+       };
+
+       main_i2c5: i2c@2050000 {
+               compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+               reg = <0x00 0x2050000 0x00 0x100>;
+               interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "fck";
+               clocks = <&k3_clks 192 1>;
+               power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
+       };
+
+       main_i2c6: i2c@2060000 {
+               compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+               reg = <0x00 0x2060000 0x00 0x100>;
+               interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "fck";
+               clocks = <&k3_clks 193 1>;
+               power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
+       };
 };

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index c168171da429cedf0cecf9bcf9c4873745fb00fd..b67b33c9bda66f99828f942ef1e9e399ec66e0e9 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -210,4 +210,37 @@
                        ti,cpts-periodic-outputs = <2>;
                };
        };
+
+       mcu_i2c0: i2c@40b00000 {
+               compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+               reg = <0x00 0x40b00000 0x00 0x100>;
+               interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "fck";
+               clocks = <&k3_clks 194 1>;
+               power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
+       };
+
+       mcu_i2c1: i2c@40b10000 {
+               compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+               reg = <0x00 0x40b10000 0x00 0x100>;
+               interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "fck";
+               clocks = <&k3_clks 195 1>;
+               power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
+       };
+
+       wkup_i2c0: i2c@42120000 {
+               compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+               reg = <0x00 0x42120000 0x00 0x100>;
+               interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "fck";
+               clocks = <&k3_clks 197 1>;
+               power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
+       };
 };