l4_fast: interconnect@4a000000 {
};
- emif: emif@4c000000 {
- compatible = "ti,emif-am4372";
- reg = <0x4c000000 0x1000000>;
- ti,hwmods = "emif";
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ target-module@4c000000 {
+ compatible = "ti,sysc-omap4-simple", "ti,sysc";
+ reg = <0x4c000000 0x4>;
+ reg-names = "rev";
+ clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>;
+ clock-names = "fck";
ti,no-idle;
- sram = <&pm_sram_code
- &pm_sram_data>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4c000000 0x1000000>;
+
+ emif: emif@0 {
+ compatible = "ti,emif-am4372";
+ reg = <0 0x1000000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ sram = <&pm_sram_code
+ &pm_sram_data>;
+ };
};
target-module@49000000 {
.clkdm_name = "l4_wkup_clkdm",
};
-/*
- * 'emif' class
- * instance(s): emif
- */
-static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
- .rev_offs = 0x0000,
-};
-
-struct omap_hwmod_class am33xx_emif_hwmod_class = {
- .name = "emif",
- .sysc = &am33xx_emif_sysc,
-};
-
-
-
/* ocmcram */
static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
.name = "ocmcram",
#include "omap_hwmod_common_data.h"
/* IP blocks */
-static struct omap_hwmod am43xx_emif_hwmod = {
- .name = "emif",
- .class = &am33xx_emif_hwmod_class,
- .clkdm_name = "emif_clkdm",
- .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "dpll_ddr_m2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
static struct omap_hwmod am43xx_l4_hs_hwmod = {
.name = "l4_hs",
.class = &am33xx_l4_hwmod_class,
};
/* Interfaces */
-static struct omap_hwmod_ocp_if am43xx_l3_main__emif = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am43xx_emif_hwmod,
- .clk = "dpll_core_m4_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
.master = &am33xx_l3_main_hwmod,
&am33xx_l3_main__l3_s,
&am33xx_l3_main__l3_instr,
&am33xx_l3_s__l3_main,
- &am43xx_l3_main__emif,
&am43xx_l4_wkup__smartreflex0,
&am43xx_l4_wkup__smartreflex1,
&am33xx_l3_main__ocmc,