drm/amdgpu: handle asics with 1 SDMA instance

This patch will handle asics with 1 SDMA instance.

Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 307a1da13557d99d7f32f45a9e01d7b0c8c06726..29acc5573f56196dee1c06465595aedc453148d0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -252,8 +252,9 @@ static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
        *value = 0;
        for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {
                en = &soc21_allowed_read_registers[i];
-               if (reg_offset !=
-                   (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
+               if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
+                       reg_offset !=
+                       (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
                        continue;
 
                *value = soc21_get_register_value(adev,