Merge tag 'pinctrl-v4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...

Pull pincontrol updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.1 development
  cycle.  Nothing really exciting this time: we basically added a few
  new drivers and subdrivers and stabilized them in linux-next.  Some
  cleanups too.  With sunrisepoint Intel has a real fine fully featured
  pin control driver for contemporary hardware, and the AMD driver is
  also for large deployments.  Most of the others are ARM devices.

  New drivers:
    - Intel Sunrisepoint
    - AMD KERNCZ GPIO
    - Broadcom Cygnus IOMUX

  New subdrivers:
    - Marvell MVEBU Armada 39x SoCs
    - Samsung Exynos 5433
    - nVidia Tegra 210
    - Mediatek MT8135
    - Mediatek MT8173
    - AMLogic Meson8b
    - Qualcomm PM8916

  On top of this cleanups and development history for the above drivers
  as issues were fixed after merging"

* tag 'pinctrl-v4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (71 commits)
  pinctrl: sirf: move sgpio lock into state container
  pinctrl: Add support for PM8916 GPIO's and MPP's
  pinctrl: bcm2835: Fix support for threaded level triggered IRQs
  sh-pfc: r8a7790: add EtherAVB pin groups
  pinctrl: Document "function" + "pins" pinmux binding
  pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support
  pinctrl: fsl: imx: Check for 0 config register
  pinctrl: Add support for Meson8b
  documentation: Extend pinctrl docs for Meson8b
  pinctrl: Cleanup Meson8 driver
  Fix inconsistent spinlock of AMD GPIO driver which can be recognized by static analysis tool smatch. Declare constant Variables with Sparse's suggestion.
  pinctrl: at91: convert __raw to endian agnostic IO
  pinctrl: constify of_device_id array
  pinctrl: pinconf-generic: add dt node names to error messages
  pinctrl: pinconf-generic: scan also referenced phandle node
  pinctrl: mvebu: add suspend/resume support to Armada XP pinctrl driver
  pinctrl: st: Display pin's function when printing pinctrl debug information
  pinctrl: st: Show correct pin direction also in GPIO mode
  pinctrl: st: Supply a GPIO get_direction() call-back
  pinctrl: st: Move st_get_pio_control() further up the source file
  ...

diff --combined drivers/pinctrl/pinctrl-at91.c
index a4814066ea0876d7f52063f5ba2cfb5ca5a6f6d3,ecf77eb3d69e56d857e69d090fe6b4cd78956fc7..2f797cb7e2050175e8b870d9caf342a623061dce
--- 1/drivers/pinctrl/pinctrl-at91.c
--- 2/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@@ -451,18 -451,18 +451,18 @@@ static enum at91_mux at91_mux_get_perip
  
  static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
  {
-       return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1;
+       return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1;
  }
  
  static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
  {
-       __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
+       writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
  }
  
  static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
  {
-       if ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1)
-               return !((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
+       if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1)
+               return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
  
        return false;
  }
@@@ -470,55 -470,55 +470,55 @@@
  static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
  {
        if (is_on)
-               __raw_writel(mask, pio + PIO_IFSCDR);
+               writel_relaxed(mask, pio + PIO_IFSCDR);
        at91_mux_set_deglitch(pio, mask, is_on);
  }
  
  static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
  {
-       *div = __raw_readl(pio + PIO_SCDR);
+       *div = readl_relaxed(pio + PIO_SCDR);
  
-       return ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) &&
-              ((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
+       return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) &&
+              ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
  }
  
  static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
                                bool is_on, u32 div)
  {
        if (is_on) {
-               __raw_writel(mask, pio + PIO_IFSCER);
-               __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
-               __raw_writel(mask, pio + PIO_IFER);
+               writel_relaxed(mask, pio + PIO_IFSCER);
+               writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
+               writel_relaxed(mask, pio + PIO_IFER);
        } else
-               __raw_writel(mask, pio + PIO_IFSCDR);
+               writel_relaxed(mask, pio + PIO_IFSCDR);
  }
  
  static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
  {
-       return !((__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1);
+       return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1);
  }
  
  static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
  {
        if (is_on)
-               __raw_writel(mask, pio + PIO_PUDR);
+               writel_relaxed(mask, pio + PIO_PUDR);
  
-       __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
+       writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
  }
  
  static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
  {
-       __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
+       writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
  }
  
  static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
  {
-       return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1;
+       return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1;
  }
  
  static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
  {
-       unsigned tmp = __raw_readl(reg);
+       unsigned tmp = readl_relaxed(reg);
  
        tmp = tmp >> two_bit_pin_value_shift_amount(pin);
  
@@@ -554,13 -554,13 +554,13 @@@ static unsigned at91_mux_sam9x5_get_dri
  
  static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
  {
-       unsigned tmp = __raw_readl(reg);
+       unsigned tmp = readl_relaxed(reg);
        unsigned shift = two_bit_pin_value_shift_amount(pin);
  
        tmp &= ~(DRIVE_STRENGTH_MASK  <<  shift);
        tmp |= strength << shift;
  
-       __raw_writel(tmp, reg);
+       writel_relaxed(tmp, reg);
  }
  
  static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
@@@ -1114,7 -1114,7 +1114,7 @@@ static int at91_pinctrl_parse_functions
        return 0;
  }
  
- static struct of_device_id at91_pinctrl_of_match[] = {
+ static const struct of_device_id at91_pinctrl_of_match[] = {
        { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
        { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
        { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
@@@ -1240,8 -1240,7 +1240,7 @@@ static int at91_pinctrl_probe(struct pl
  
        if (!info->pctl) {
                dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
-               ret = -EINVAL;
-               goto err;
+               return -EINVAL;
        }
  
        /* We will handle a range of GPIO pins */
@@@ -1252,9 -1251,6 +1251,6 @@@
        dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
  
        return 0;
- 
- err:
-       return ret;
  }
  
  static int at91_pinctrl_remove(struct platform_device *pdev)
@@@ -1477,25 -1473,28 +1473,25 @@@ static void gpio_irq_ack(struct irq_dat
        /* the interrupt is already cleared before by reading ISR */
  }
  
 -static unsigned int gpio_irq_startup(struct irq_data *d)
 +static int gpio_irq_request_res(struct irq_data *d)
  {
        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
        unsigned        pin = d->hwirq;
        int ret;
  
        ret = gpiochip_lock_as_irq(&at91_gpio->chip, pin);
 -      if (ret) {
 +      if (ret)
                dev_err(at91_gpio->chip.dev, "unable to lock pind %lu IRQ\n",
                        d->hwirq);
 -              return ret;
 -      }
 -      gpio_irq_unmask(d);
 -      return 0;
 +
 +      return ret;
  }
  
 -static void gpio_irq_shutdown(struct irq_data *d)
 +static void gpio_irq_release_res(struct irq_data *d)
  {
        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
        unsigned        pin = d->hwirq;
  
 -      gpio_irq_mask(d);
        gpiochip_unlock_as_irq(&at91_gpio->chip, pin);
  }
  
@@@ -1535,9 -1534,9 +1531,9 @@@ void at91_pinctrl_gpio_suspend(void
  
                pio = gpio_chips[i]->regbase;
  
-               backups[i] = __raw_readl(pio + PIO_IMR);
-               __raw_writel(backups[i], pio + PIO_IDR);
-               __raw_writel(wakeups[i], pio + PIO_IER);
+               backups[i] = readl_relaxed(pio + PIO_IMR);
+               writel_relaxed(backups[i], pio + PIO_IDR);
+               writel_relaxed(wakeups[i], pio + PIO_IER);
  
                if (!wakeups[i])
                        clk_disable_unprepare(gpio_chips[i]->clock);
@@@ -1562,8 -1561,8 +1558,8 @@@ void at91_pinctrl_gpio_resume(void
                if (!wakeups[i])
                        clk_prepare_enable(gpio_chips[i]->clock);
  
-               __raw_writel(wakeups[i], pio + PIO_IDR);
-               __raw_writel(backups[i], pio + PIO_IER);
+               writel_relaxed(wakeups[i], pio + PIO_IDR);
+               writel_relaxed(backups[i], pio + PIO_IER);
        }
  }
  
@@@ -1574,8 -1573,8 +1570,8 @@@
  static struct irq_chip gpio_irqchip = {
        .name           = "GPIO",
        .irq_ack        = gpio_irq_ack,
 -      .irq_startup    = gpio_irq_startup,
 -      .irq_shutdown   = gpio_irq_shutdown,
 +      .irq_request_resources = gpio_irq_request_res,
 +      .irq_release_resources = gpio_irq_release_res,
        .irq_disable    = gpio_irq_mask,
        .irq_mask       = gpio_irq_mask,
        .irq_unmask     = gpio_irq_unmask,
@@@ -1694,7 -1693,7 +1690,7 @@@ static struct gpio_chip at91_gpio_templ
        .ngpio                  = MAX_NB_GPIO_PER_BANK,
  };
  
- static struct of_device_id at91_gpio_of_match[] = {
+ static const struct of_device_id at91_gpio_of_match[] = {
        { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
        { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
        { /* sentinel */ }

diff --combined drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index 3c68a8e5e0dd4d4bbb8d6fae4166a6bf92e521a2,37aa2a8bd4f6ef5888fb8c707a7ad172f82cc417..7376a97b5e65c3f27471c6a2fc90848144d507ce
--- 1/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
--- 2/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@@ -1011,7 -1011,6 +1011,7 @@@ static const struct sunxi_pinctrl_desc 
        .pins = sun4i_a10_pins,
        .npins = ARRAY_SIZE(sun4i_a10_pins),
        .irq_banks = 1,
 +      .irq_read_needs_mux = true,
  };
  
  static int sun4i_a10_pinctrl_probe(struct platform_device *pdev)
@@@ -1020,7 -1019,7 +1020,7 @@@
                                  &sun4i_a10_pinctrl_data);
  }
  
- static struct of_device_id sun4i_a10_pinctrl_match[] = {
+ static const struct of_device_id sun4i_a10_pinctrl_match[] = {
        { .compatible = "allwinner,sun4i-a10-pinctrl", },
        {}
  };