TCGv_i32 sar_m32;
unsigned window;
+ bool cwoe;
bool debug;
bool icount;
tcg_temp_free(tmp);
}
-static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
+static bool check_sr(DisasContext *dc, uint32_t sr, unsigned access)
{
if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
if (sregnames[sr].name) {
} else {
qemu_log_mask(LOG_UNIMP, "SR %d is not implemented\n", sr);
}
- gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
return false;
} else if (!(sregnames[sr].access & access)) {
static const char * const access_text[] = {
assert(access < ARRAY_SIZE(access_text) && access_text[access]);
qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not available for %s\n", sregnames[sr].name,
access_text[access]);
- gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
return false;
}
return true;
xtensa_format fmt;
int slot, slots;
unsigned i;
+ uint32_t op_flags = 0;
+ struct {
+ XtensaOpcodeOps *ops;
+ uint32_t arg[MAX_OPCODE_ARGS];
+ uint32_t raw_arg[MAX_OPCODE_ARGS];
+ } slot_prop[MAX_INSN_SLOTS];
if (len == XTENSA_UNDEFINED) {
qemu_log_mask(LOG_GUEST_ERROR,
for (slot = 0; slot < slots; ++slot) {
xtensa_opcode opc;
int opnd, vopnd, opnds;
- uint32_t raw_arg[MAX_OPCODE_ARGS];
- uint32_t arg[MAX_OPCODE_ARGS];
+ uint32_t *raw_arg = slot_prop[slot].raw_arg;
+ uint32_t *arg = slot_prop[slot].arg;
XtensaOpcodeOps *ops;
dc->raw_arg = raw_arg;
}
}
ops = dc->config->opcode_ops[opc];
+ slot_prop[slot].ops = ops;
+
if (ops) {
- ops->translate(dc, arg, ops->par);
+ op_flags |= ops->op_flags;
} else {
- qemu_log_mask(LOG_GUEST_ERROR,
+ qemu_log_mask(LOG_UNIMP,
"unimplemented opcode '%s' in slot %d (pc = %08x)\n",
xtensa_opcode_name(isa, opc), slot, dc->pc);
+ op_flags |= XTENSA_OP_ILL;
+ }
+ if ((op_flags & XTENSA_OP_ILL) ||
+ (ops && ops->test_ill && ops->test_ill(dc, arg, ops->par))) {
gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
return;
}
}
+
+ for (slot = 0; slot < slots; ++slot) {
+ XtensaOpcodeOps *ops = slot_prop[slot].ops;
+
+ dc->raw_arg = slot_prop[slot].raw_arg;
+ ops->translate(dc, slot_prop[slot].arg, ops->par);
+ }
if (dc->base.is_jmp == DISAS_NEXT) {
gen_check_loop_end(dc, 0);
}
XTENSA_TBFLAG_CPENABLE_SHIFT;
dc->window = ((tb_flags & XTENSA_TBFLAG_WINDOW_MASK) >>
XTENSA_TBFLAG_WINDOW_SHIFT);
+ dc->cwoe = tb_flags & XTENSA_TBFLAG_CWOE;
if (dc->config->isa) {
dc->insnbuf = xtensa_insnbuf_alloc(dc->config->isa);
}
}
+static bool test_ill_entry(DisasContext *dc, const uint32_t arg[],
+ const uint32_t par[])
+{
+ if (arg[0] > 3 || !dc->cwoe) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Illegal entry instruction(pc = %08x)\n", dc->pc);
+ return true;
+ } else {
+ return false;
+ }
+}
+
static void translate_entry(DisasContext *dc, const uint32_t arg[],
const uint32_t par[])
{
}
}
-static void translate_ill(DisasContext *dc, const uint32_t arg[],
- const uint32_t par[])
-{
- gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
-}
-
static void translate_j(DisasContext *dc, const uint32_t arg[],
const uint32_t par[])
{
gen_jump(dc, cpu_R[0]);
}
+static bool test_ill_retw(DisasContext *dc, const uint32_t arg[],
+ const uint32_t par[])
+{
+ if (!dc->cwoe) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Illegal retw instruction(pc = %08x)\n", dc->pc);
+ return true;
+ } else {
+ TCGv_i32 tmp = tcg_const_i32(dc->pc);
+
+ gen_helper_test_ill_retw(cpu_env, tmp);
+ tcg_temp_free(tmp);
+ return false;
+ }
+}
+
static void translate_retw(DisasContext *dc, const uint32_t arg[],
const uint32_t par[])
{
}
}
+static bool test_ill_rsr(DisasContext *dc, const uint32_t arg[],
+ const uint32_t par[])
+{
+ return !check_sr(dc, par[0], SR_R);
+}
+
static void translate_rsr(DisasContext *dc, const uint32_t arg[],
const uint32_t par[])
{
- if (gen_check_sr(dc, par[0], SR_R) &&
- (par[0] < 64 || gen_check_privilege(dc)) &&
+ if ((par[0] < 64 || gen_check_privilege(dc)) &&
gen_window_check1(dc, arg[0])) {
if (gen_rsr(dc, cpu_R[arg[0]], par[0])) {
gen_jumpi_check_loop_end(dc, 0);
}
}
+static bool test_ill_simcall(DisasContext *dc, const uint32_t arg[],
+ const uint32_t par[])
+{
+#ifdef CONFIG_USER_ONLY
+ bool ill = true;
+#else
+ bool ill = !semihosting_enabled();
+#endif
+ if (ill) {
+ qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
+ }
+ return ill;
+}
+
static void translate_simcall(DisasContext *dc, const uint32_t arg[],
const uint32_t par[])
{
#ifndef CONFIG_USER_ONLY
- if (semihosting_enabled()) {
- if (gen_check_privilege(dc)) {
- gen_helper_simcall(cpu_env);
- }
- } else
-#endif
- {
- qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
- gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
+ if (gen_check_privilege(dc)) {
+ gen_helper_simcall(cpu_env);
}
+#endif
}
/*
}
}
+static bool test_ill_wsr(DisasContext *dc, const uint32_t arg[],
+ const uint32_t par[])
+{
+ return !check_sr(dc, par[0], SR_W);
+}
+
static void translate_wsr(DisasContext *dc, const uint32_t arg[],
const uint32_t par[])
{
- if (gen_check_sr(dc, par[0], SR_W) &&
- (par[0] < 64 || gen_check_privilege(dc)) &&
+ if ((par[0] < 64 || gen_check_privilege(dc)) &&
gen_window_check1(dc, arg[0])) {
gen_wsr(dc, par[0], cpu_R[arg[0]]);
}
}
}
+static bool test_ill_xsr(DisasContext *dc, const uint32_t arg[],
+ const uint32_t par[])
+{
+ return !check_sr(dc, par[0], SR_X);
+}
+
static void translate_xsr(DisasContext *dc, const uint32_t arg[],
const uint32_t par[])
{
- if (gen_check_sr(dc, par[0], SR_X) &&
- (par[0] < 64 || gen_check_privilege(dc)) &&
+ if ((par[0] < 64 || gen_check_privilege(dc)) &&
gen_window_check1(dc, arg[0])) {
TCGv_i32 tmp = tcg_temp_new_i32();
bool rsr_end, wsr_end;
}, {
.name = "entry",
.translate = translate_entry,
+ .test_ill = test_ill_entry,
}, {
.name = "esync",
.translate = translate_nop,
.translate = translate_memw,
}, {
.name = "hwwdtlba",
- .translate = translate_ill,
+ .op_flags = XTENSA_OP_ILL,
}, {
.name = "hwwitlba",
- .translate = translate_ill,
+ .op_flags = XTENSA_OP_ILL,
}, {
.name = "idtlb",
.translate = translate_itlb,
.par = (const uint32_t[]){true, false},
}, {
.name = "ill",
- .translate = translate_ill,
+ .op_flags = XTENSA_OP_ILL,
}, {
.name = "ill.n",
- .translate = translate_ill,
+ .op_flags = XTENSA_OP_ILL,
}, {
.name = "ipf",
.translate = translate_icache,
.par = (const uint32_t[]){MAC16_NONE, 0, 0, 4},
}, {
.name = "ldpte",
- .translate = translate_ill,
+ .op_flags = XTENSA_OP_ILL,
}, {
.name = "loop",
.translate = translate_loop,
}, {
.name = "retw",
.translate = translate_retw,
+ .test_ill = test_ill_retw,
}, {
.name = "retw.n",
.translate = translate_retw,
+ .test_ill = test_ill_retw,
}, {
.name = "rfdd",
- .translate = translate_ill,
+ .op_flags = XTENSA_OP_ILL,
}, {
.name = "rfde",
.translate = translate_rfde,
}, {
.name = "rfdo",
- .translate = translate_ill,
+ .op_flags = XTENSA_OP_ILL,
}, {
.name = "rfe",
.translate = translate_rfe,
}, {
.name = "rsr.176",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){176},
}, {
.name = "rsr.208",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){208},
}, {
.name = "rsr.acchi",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){ACCHI},
}, {
.name = "rsr.acclo",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){ACCLO},
}, {
.name = "rsr.atomctl",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){ATOMCTL},
}, {
.name = "rsr.br",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){BR},
}, {
.name = "rsr.cacheattr",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){CACHEATTR},
}, {
.name = "rsr.ccompare0",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){CCOMPARE},
}, {
.name = "rsr.ccompare1",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){CCOMPARE + 1},
}, {
.name = "rsr.ccompare2",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){CCOMPARE + 2},
}, {
.name = "rsr.ccount",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){CCOUNT},
}, {
.name = "rsr.configid0",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){CONFIGID0},
}, {
.name = "rsr.configid1",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){CONFIGID1},
}, {
.name = "rsr.cpenable",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){CPENABLE},
}, {
.name = "rsr.dbreaka0",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){DBREAKA},
}, {
.name = "rsr.dbreaka1",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){DBREAKA + 1},
}, {
.name = "rsr.dbreakc0",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){DBREAKC},
}, {
.name = "rsr.dbreakc1",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){DBREAKC + 1},
}, {
.name = "rsr.ddr",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){DDR},
}, {
.name = "rsr.debugcause",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){DEBUGCAUSE},
}, {
.name = "rsr.depc",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){DEPC},
}, {
.name = "rsr.dtlbcfg",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){DTLBCFG},
}, {
.name = "rsr.epc1",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EPC1},
}, {
.name = "rsr.epc2",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EPC1 + 1},
}, {
.name = "rsr.epc3",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EPC1 + 2},
}, {
.name = "rsr.epc4",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EPC1 + 3},
}, {
.name = "rsr.epc5",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EPC1 + 4},
}, {
.name = "rsr.epc6",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EPC1 + 5},
}, {
.name = "rsr.epc7",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EPC1 + 6},
}, {
.name = "rsr.eps2",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EPS2},
}, {
.name = "rsr.eps3",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EPS2 + 1},
}, {
.name = "rsr.eps4",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EPS2 + 2},
}, {
.name = "rsr.eps5",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EPS2 + 3},
}, {
.name = "rsr.eps6",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EPS2 + 4},
}, {
.name = "rsr.eps7",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EPS2 + 5},
}, {
.name = "rsr.exccause",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EXCCAUSE},
}, {
.name = "rsr.excsave1",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EXCSAVE1},
}, {
.name = "rsr.excsave2",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EXCSAVE1 + 1},
}, {
.name = "rsr.excsave3",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EXCSAVE1 + 2},
}, {
.name = "rsr.excsave4",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EXCSAVE1 + 3},
}, {
.name = "rsr.excsave5",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EXCSAVE1 + 4},
}, {
.name = "rsr.excsave6",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EXCSAVE1 + 5},
}, {
.name = "rsr.excsave7",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EXCSAVE1 + 6},
}, {
.name = "rsr.excvaddr",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){EXCVADDR},
}, {
.name = "rsr.ibreaka0",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){IBREAKA},
}, {
.name = "rsr.ibreaka1",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){IBREAKA + 1},
}, {
.name = "rsr.ibreakenable",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){IBREAKENABLE},
}, {
.name = "rsr.icount",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){ICOUNT},
}, {
.name = "rsr.icountlevel",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){ICOUNTLEVEL},
}, {
.name = "rsr.intclear",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){INTCLEAR},
}, {
.name = "rsr.intenable",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){INTENABLE},
}, {
.name = "rsr.interrupt",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){INTSET},
}, {
.name = "rsr.intset",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){INTSET},
}, {
.name = "rsr.itlbcfg",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){ITLBCFG},
}, {
.name = "rsr.lbeg",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){LBEG},
}, {
.name = "rsr.lcount",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){LCOUNT},
}, {
.name = "rsr.lend",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){LEND},
}, {
.name = "rsr.litbase",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){LITBASE},
}, {
.name = "rsr.m0",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){MR},
}, {
.name = "rsr.m1",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){MR + 1},
}, {
.name = "rsr.m2",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){MR + 2},
}, {
.name = "rsr.m3",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){MR + 3},
}, {
.name = "rsr.memctl",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){MEMCTL},
}, {
.name = "rsr.misc0",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){MISC},
}, {
.name = "rsr.misc1",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){MISC + 1},
}, {
.name = "rsr.misc2",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){MISC + 2},
}, {
.name = "rsr.misc3",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){MISC + 3},
}, {
.name = "rsr.prid",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){PRID},
}, {
.name = "rsr.ps",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){PS},
}, {
.name = "rsr.ptevaddr",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){PTEVADDR},
}, {
.name = "rsr.rasid",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){RASID},
}, {
.name = "rsr.sar",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){SAR},
}, {
.name = "rsr.scompare1",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){SCOMPARE1},
}, {
.name = "rsr.vecbase",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){VECBASE},
}, {
.name = "rsr.windowbase",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){WINDOW_BASE},
}, {
.name = "rsr.windowstart",
.translate = translate_rsr,
+ .test_ill = test_ill_rsr,
.par = (const uint32_t[]){WINDOW_START},
}, {
.name = "rsync",
}, {
.name = "simcall",
.translate = translate_simcall,
+ .test_ill = test_ill_simcall,
}, {
.name = "sll",
.translate = translate_sll,
}, {
.name = "wsr.176",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){176},
}, {
.name = "wsr.208",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){208},
}, {
.name = "wsr.acchi",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){ACCHI},
}, {
.name = "wsr.acclo",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){ACCLO},
}, {
.name = "wsr.atomctl",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){ATOMCTL},
}, {
.name = "wsr.br",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){BR},
}, {
.name = "wsr.cacheattr",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){CACHEATTR},
}, {
.name = "wsr.ccompare0",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){CCOMPARE},
}, {
.name = "wsr.ccompare1",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){CCOMPARE + 1},
}, {
.name = "wsr.ccompare2",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){CCOMPARE + 2},
}, {
.name = "wsr.ccount",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){CCOUNT},
}, {
.name = "wsr.configid0",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){CONFIGID0},
}, {
.name = "wsr.configid1",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){CONFIGID1},
}, {
.name = "wsr.cpenable",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){CPENABLE},
}, {
.name = "wsr.dbreaka0",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){DBREAKA},
}, {
.name = "wsr.dbreaka1",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){DBREAKA + 1},
}, {
.name = "wsr.dbreakc0",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){DBREAKC},
}, {
.name = "wsr.dbreakc1",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){DBREAKC + 1},
}, {
.name = "wsr.ddr",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){DDR},
}, {
.name = "wsr.debugcause",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){DEBUGCAUSE},
}, {
.name = "wsr.depc",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){DEPC},
}, {
.name = "wsr.dtlbcfg",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){DTLBCFG},
}, {
.name = "wsr.epc1",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EPC1},
}, {
.name = "wsr.epc2",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EPC1 + 1},
}, {
.name = "wsr.epc3",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EPC1 + 2},
}, {
.name = "wsr.epc4",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EPC1 + 3},
}, {
.name = "wsr.epc5",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EPC1 + 4},
}, {
.name = "wsr.epc6",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EPC1 + 5},
}, {
.name = "wsr.epc7",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EPC1 + 6},
}, {
.name = "wsr.eps2",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EPS2},
}, {
.name = "wsr.eps3",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EPS2 + 1},
}, {
.name = "wsr.eps4",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EPS2 + 2},
}, {
.name = "wsr.eps5",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EPS2 + 3},
}, {
.name = "wsr.eps6",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EPS2 + 4},
}, {
.name = "wsr.eps7",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EPS2 + 5},
}, {
.name = "wsr.exccause",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EXCCAUSE},
}, {
.name = "wsr.excsave1",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EXCSAVE1},
}, {
.name = "wsr.excsave2",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EXCSAVE1 + 1},
}, {
.name = "wsr.excsave3",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EXCSAVE1 + 2},
}, {
.name = "wsr.excsave4",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EXCSAVE1 + 3},
}, {
.name = "wsr.excsave5",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EXCSAVE1 + 4},
}, {
.name = "wsr.excsave6",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EXCSAVE1 + 5},
}, {
.name = "wsr.excsave7",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EXCSAVE1 + 6},
}, {
.name = "wsr.excvaddr",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){EXCVADDR},
}, {
.name = "wsr.ibreaka0",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){IBREAKA},
}, {
.name = "wsr.ibreaka1",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){IBREAKA + 1},
}, {
.name = "wsr.ibreakenable",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){IBREAKENABLE},
}, {
.name = "wsr.icount",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){ICOUNT},
}, {
.name = "wsr.icountlevel",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){ICOUNTLEVEL},
}, {
.name = "wsr.intclear",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){INTCLEAR},
}, {
.name = "wsr.intenable",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){INTENABLE},
}, {
.name = "wsr.interrupt",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){INTSET},
}, {
.name = "wsr.intset",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){INTSET},
}, {
.name = "wsr.itlbcfg",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){ITLBCFG},
}, {
.name = "wsr.lbeg",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){LBEG},
}, {
.name = "wsr.lcount",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){LCOUNT},
}, {
.name = "wsr.lend",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){LEND},
}, {
.name = "wsr.litbase",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){LITBASE},
}, {
.name = "wsr.m0",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){MR},
}, {
.name = "wsr.m1",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){MR + 1},
}, {
.name = "wsr.m2",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){MR + 2},
}, {
.name = "wsr.m3",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){MR + 3},
}, {
.name = "wsr.memctl",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){MEMCTL},
}, {
.name = "wsr.misc0",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){MISC},
}, {
.name = "wsr.misc1",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){MISC + 1},
}, {
.name = "wsr.misc2",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){MISC + 2},
}, {
.name = "wsr.misc3",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){MISC + 3},
}, {
.name = "wsr.mmid",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){MMID},
}, {
.name = "wsr.prid",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){PRID},
}, {
.name = "wsr.ps",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){PS},
}, {
.name = "wsr.ptevaddr",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){PTEVADDR},
}, {
.name = "wsr.rasid",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){RASID},
}, {
.name = "wsr.sar",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){SAR},
}, {
.name = "wsr.scompare1",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){SCOMPARE1},
}, {
.name = "wsr.vecbase",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){VECBASE},
}, {
.name = "wsr.windowbase",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){WINDOW_BASE},
}, {
.name = "wsr.windowstart",
.translate = translate_wsr,
+ .test_ill = test_ill_wsr,
.par = (const uint32_t[]){WINDOW_START},
}, {
.name = "wur.expstate",
}, {
.name = "xsr.176",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){176},
}, {
.name = "xsr.208",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){208},
}, {
.name = "xsr.acchi",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){ACCHI},
}, {
.name = "xsr.acclo",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){ACCLO},
}, {
.name = "xsr.atomctl",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){ATOMCTL},
}, {
.name = "xsr.br",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){BR},
}, {
.name = "xsr.cacheattr",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){CACHEATTR},
}, {
.name = "xsr.ccompare0",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){CCOMPARE},
}, {
.name = "xsr.ccompare1",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){CCOMPARE + 1},
}, {
.name = "xsr.ccompare2",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){CCOMPARE + 2},
}, {
.name = "xsr.ccount",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){CCOUNT},
}, {
.name = "xsr.configid0",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){CONFIGID0},
}, {
.name = "xsr.configid1",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){CONFIGID1},
}, {
.name = "xsr.cpenable",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){CPENABLE},
}, {
.name = "xsr.dbreaka0",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){DBREAKA},
}, {
.name = "xsr.dbreaka1",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){DBREAKA + 1},
}, {
.name = "xsr.dbreakc0",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){DBREAKC},
}, {
.name = "xsr.dbreakc1",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){DBREAKC + 1},
}, {
.name = "xsr.ddr",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){DDR},
}, {
.name = "xsr.debugcause",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){DEBUGCAUSE},
}, {
.name = "xsr.depc",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){DEPC},
}, {
.name = "xsr.dtlbcfg",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){DTLBCFG},
}, {
.name = "xsr.epc1",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EPC1},
}, {
.name = "xsr.epc2",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EPC1 + 1},
}, {
.name = "xsr.epc3",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EPC1 + 2},
}, {
.name = "xsr.epc4",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EPC1 + 3},
}, {
.name = "xsr.epc5",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EPC1 + 4},
}, {
.name = "xsr.epc6",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EPC1 + 5},
}, {
.name = "xsr.epc7",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EPC1 + 6},
}, {
.name = "xsr.eps2",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EPS2},
}, {
.name = "xsr.eps3",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EPS2 + 1},
}, {
.name = "xsr.eps4",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EPS2 + 2},
}, {
.name = "xsr.eps5",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EPS2 + 3},
}, {
.name = "xsr.eps6",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EPS2 + 4},
}, {
.name = "xsr.eps7",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EPS2 + 5},
}, {
.name = "xsr.exccause",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EXCCAUSE},
}, {
.name = "xsr.excsave1",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EXCSAVE1},
}, {
.name = "xsr.excsave2",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EXCSAVE1 + 1},
}, {
.name = "xsr.excsave3",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EXCSAVE1 + 2},
}, {
.name = "xsr.excsave4",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EXCSAVE1 + 3},
}, {
.name = "xsr.excsave5",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EXCSAVE1 + 4},
}, {
.name = "xsr.excsave6",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EXCSAVE1 + 5},
}, {
.name = "xsr.excsave7",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EXCSAVE1 + 6},
}, {
.name = "xsr.excvaddr",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){EXCVADDR},
}, {
.name = "xsr.ibreaka0",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){IBREAKA},
}, {
.name = "xsr.ibreaka1",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){IBREAKA + 1},
}, {
.name = "xsr.ibreakenable",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){IBREAKENABLE},
}, {
.name = "xsr.icount",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){ICOUNT},
}, {
.name = "xsr.icountlevel",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){ICOUNTLEVEL},
}, {
.name = "xsr.intclear",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){INTCLEAR},
}, {
.name = "xsr.intenable",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){INTENABLE},
}, {
.name = "xsr.interrupt",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){INTSET},
}, {
.name = "xsr.intset",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){INTSET},
}, {
.name = "xsr.itlbcfg",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){ITLBCFG},
}, {
.name = "xsr.lbeg",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){LBEG},
}, {
.name = "xsr.lcount",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){LCOUNT},
}, {
.name = "xsr.lend",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){LEND},
}, {
.name = "xsr.litbase",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){LITBASE},
}, {
.name = "xsr.m0",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){MR},
}, {
.name = "xsr.m1",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){MR + 1},
}, {
.name = "xsr.m2",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){MR + 2},
}, {
.name = "xsr.m3",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){MR + 3},
}, {
.name = "xsr.memctl",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){MEMCTL},
}, {
.name = "xsr.misc0",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){MISC},
}, {
.name = "xsr.misc1",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){MISC + 1},
}, {
.name = "xsr.misc2",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){MISC + 2},
}, {
.name = "xsr.misc3",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){MISC + 3},
}, {
.name = "xsr.prid",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){PRID},
}, {
.name = "xsr.ps",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){PS},
}, {
.name = "xsr.ptevaddr",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){PTEVADDR},
}, {
.name = "xsr.rasid",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){RASID},
}, {
.name = "xsr.sar",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){SAR},
}, {
.name = "xsr.scompare1",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){SCOMPARE1},
}, {
.name = "xsr.vecbase",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){VECBASE},
}, {
.name = "xsr.windowbase",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){WINDOW_BASE},
}, {
.name = "xsr.windowstart",
.translate = translate_xsr,
+ .test_ill = test_ill_xsr,
.par = (const uint32_t[]){WINDOW_START},
},
};