]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/commitdiff
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
authorJohn W. Linville <linville@tuxdriver.com>
Thu, 2 Dec 2010 20:46:37 +0000 (15:46 -0500)
committerJohn W. Linville <linville@tuxdriver.com>
Thu, 2 Dec 2010 20:46:37 +0000 (15:46 -0500)
Conflicts:
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

14 files changed:
1  2 
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
drivers/net/wireless/ath/ath9k/ath9k.h
drivers/net/wireless/ath/ath9k/eeprom.h
drivers/net/wireless/ath/ath9k/eeprom_def.c
drivers/net/wireless/ath/ath9k/hw.c
drivers/net/wireless/ath/ath9k/init.c
drivers/net/wireless/ath/ath9k/main.c
drivers/net/wireless/ath/ath9k/reg.h
drivers/net/wireless/ath/carl9170/main.c
drivers/net/wireless/ath/carl9170/tx.c
drivers/net/wireless/libertas/main.c
net/mac80211/rx.c
net/mac80211/tx.c

index 4aecc10cb3a698758d395a6d564fdcf05c31404c,a7b82f0085d2e899da46f6139dcac2185b42f924..872b1a3b21c68f4512dda985b8576566e16a4d72
  #define COMP_CKSUM_LEN 2
  
  #define AR_CH0_TOP (0x00016288)
 -#define AR_CH0_TOP_XPABIASLVL (0x3)
 +#define AR_CH0_TOP_XPABIASLVL (0x300)
  #define AR_CH0_TOP_XPABIASLVL_S (8)
  
  #define AR_CH0_THERM (0x00016290)
 -#define AR_CH0_THERM_SPARE (0x3f)
 -#define AR_CH0_THERM_SPARE_S (0)
 +#define AR_CH0_THERM_XPABIASLVL_MSB 0x3
 +#define AR_CH0_THERM_XPABIASLVL_MSB_S 0
 +#define AR_CH0_THERM_XPASHORT2GND 0x4
 +#define AR_CH0_THERM_XPASHORT2GND_S 2
  
  #define AR_SWITCH_TABLE_COM_ALL (0xffff)
  #define AR_SWITCH_TABLE_COM_ALL_S (0)
  #define SUB_NUM_CTL_MODES_AT_5G_40 2    /* excluding HT40, EXT-OFDM */
  #define SUB_NUM_CTL_MODES_AT_2G_40 3    /* excluding HT40, EXT-OFDM, EXT-CCK */
  
+ #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
 +static int ar9003_hw_power_interpolate(int32_t x,
 +                                     int32_t *px, int32_t *py, u_int16_t np);
++
  static const struct ar9300_eeprom ar9300_default = {
        .eepromVersion = 2,
 -      .templateVersion = 2,
 -      .macAddr = {1, 2, 3, 4, 5, 6},
 -      .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 -                   0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 +      .templateVersion = 2,
 +      .macAddr = {1, 2, 3, 4, 5, 6},
 +      .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 +                   0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
 +      .baseEepHeader = {
 +              .regDmn = { LE16(0), LE16(0x1f) },
 +              .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
 +              .opCapFlags = {
 +                      .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
 +                      .eepMisc = 0,
 +              },
 +              .rfSilent = 0,
 +              .blueToothOptions = 0,
 +              .deviceCap = 0,
 +              .deviceType = 5, /* takes lower byte in eeprom location */
 +              .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
 +              .params_for_tuning_caps = {0, 0},
 +              .featureEnable = 0x0c,
 +               /*
 +                * bit0 - enable tx temp comp - disabled
 +                * bit1 - enable tx volt comp - disabled
 +                * bit2 - enable fastClock - enabled
 +                * bit3 - enable doubling - enabled
 +                * bit4 - enable internal regulator - disabled
 +                * bit5 - enable pa predistortion - disabled
 +                */
 +              .miscConfiguration = 0, /* bit0 - turn down drivestrength */
 +              .eepromWriteEnableGpio = 3,
 +              .wlanDisableGpio = 0,
 +              .wlanLedGpio = 8,
 +              .rxBandSelectGpio = 0xff,
 +              .txrxgain = 0,
 +              .swreg = 0,
 +       },
 +      .modalHeader2G = {
 +      /* ar9300_modal_eep_header  2g */
 +              /* 4 idle,t1,t2,b(4 bits per setting) */
 +              .antCtrlCommon = LE32(0x110),
 +              /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 +              .antCtrlCommon2 = LE32(0x22222),
 +
 +              /*
 +               * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
 +               * rx1, rx12, b (2 bits each)
 +               */
 +              .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
 +
 +              /*
 +               * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
 +               * for ar9280 (0xa20c/b20c 5:0)
 +               */
 +              .xatten1DB = {0, 0, 0},
 +
 +              /*
 +               * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 +               * for ar9280 (0xa20c/b20c 16:12
 +               */
 +              .xatten1Margin = {0, 0, 0},
 +              .tempSlope = 36,
 +              .voltSlope = 0,
 +
 +              /*
 +               * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 +               * channels in usual fbin coding format
 +               */
 +              .spurChans = {0, 0, 0, 0, 0},
 +
 +              /*
 +               * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 +               * if the register is per chain
 +               */
 +              .noiseFloorThreshCh = {-1, 0, 0},
 +              .ob = {1, 1, 1},/* 3 chain */
 +              .db_stage2 = {1, 1, 1}, /* 3 chain  */
 +              .db_stage3 = {0, 0, 0},
 +              .db_stage4 = {0, 0, 0},
 +              .xpaBiasLvl = 0,
 +              .txFrameToDataStart = 0x0e,
 +              .txFrameToPaOn = 0x0e,
 +              .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 +              .antennaGain = 0,
 +              .switchSettling = 0x2c,
 +              .adcDesiredSize = -30,
 +              .txEndToXpaOff = 0,
 +              .txEndToRxOn = 0x2,
 +              .txFrameToXpaOn = 0xe,
 +              .thresh62 = 28,
 +              .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 +              .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 +              .futureModal = {
 +                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 +              },
 +       },
 +      .base_ext1 = {
 +              .ant_div_control = 0,
 +              .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 +      },
 +      .calFreqPier2G = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2437, 1),
 +              FREQ2FBIN(2472, 1),
 +       },
 +      /* ar9300_cal_data_per_freq_op_loop 2g */
 +      .calPierData2G = {
 +              { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 +              { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 +              { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 +       },
 +      .calTarget_freqbin_Cck = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2484, 1),
 +       },
 +      .calTarget_freqbin_2G = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2437, 1),
 +              FREQ2FBIN(2472, 1)
 +       },
 +      .calTarget_freqbin_2GHT20 = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2437, 1),
 +              FREQ2FBIN(2472, 1)
 +       },
 +      .calTarget_freqbin_2GHT40 = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2437, 1),
 +              FREQ2FBIN(2472, 1)
 +       },
 +      .calTargetPowerCck = {
 +               /* 1L-5L,5S,11L,11S */
 +               { {36, 36, 36, 36} },
 +               { {36, 36, 36, 36} },
 +      },
 +      .calTargetPower2G = {
 +               /* 6-24,36,48,54 */
 +               { {32, 32, 28, 24} },
 +               { {32, 32, 28, 24} },
 +               { {32, 32, 28, 24} },
 +      },
 +      .calTargetPower2GHT20 = {
 +              { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 +              { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 +              { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 +      },
 +      .calTargetPower2GHT40 = {
 +              { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 +              { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 +              { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 +      },
 +      .ctlIndex_2G =  {
 +              0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 +              0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 +      },
 +      .ctl_freqbin_2G = {
 +              {
 +                      FREQ2FBIN(2412, 1),
 +                      FREQ2FBIN(2417, 1),
 +                      FREQ2FBIN(2457, 1),
 +                      FREQ2FBIN(2462, 1)
 +              },
 +              {
 +                      FREQ2FBIN(2412, 1),
 +                      FREQ2FBIN(2417, 1),
 +                      FREQ2FBIN(2462, 1),
 +                      0xFF,
 +              },
 +
 +              {
 +                      FREQ2FBIN(2412, 1),
 +                      FREQ2FBIN(2417, 1),
 +                      FREQ2FBIN(2462, 1),
 +                      0xFF,
 +              },
 +              {
 +                      FREQ2FBIN(2422, 1),
 +                      FREQ2FBIN(2427, 1),
 +                      FREQ2FBIN(2447, 1),
 +                      FREQ2FBIN(2452, 1)
 +              },
 +
 +              {
 +                      /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 +                      /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 +              },
 +
 +              {
 +                      /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 +                      0,
 +              },
 +
 +              {
 +                      /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 +                      FREQ2FBIN(2472, 1),
 +                      0,
 +              },
 +
 +              {
 +                      /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 +                      /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 +                      /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 +                      /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 +              },
 +
 +              {
 +                      /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 +              },
 +
 +              {
 +                      /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 +                      0
 +              },
 +
 +              {
 +                      /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 +                      0
 +              },
 +
 +              {
 +                      /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 +                      /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 +                      /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 +                      /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 +              }
 +       },
 +      .ctlPowerData_2G = {
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++               { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 +
-                { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++               { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 +
-                { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 +
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
-                { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 +       },
 +      .modalHeader5G = {
 +              /* 4 idle,t1,t2,b (4 bits per setting) */
 +              .antCtrlCommon = LE32(0x110),
 +              /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 +              .antCtrlCommon2 = LE32(0x22222),
 +               /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 +              .antCtrlChain = {
 +                      LE16(0x000), LE16(0x000), LE16(0x000),
 +              },
 +               /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 +              .xatten1DB = {0, 0, 0},
 +
 +              /*
 +               * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 +               * for merlin (0xa20c/b20c 16:12
 +               */
 +              .xatten1Margin = {0, 0, 0},
 +              .tempSlope = 68,
 +              .voltSlope = 0,
 +              /* spurChans spur channels in usual fbin coding format */
 +              .spurChans = {0, 0, 0, 0, 0},
 +              /* noiseFloorThreshCh Check if the register is per chain */
 +              .noiseFloorThreshCh = {-1, 0, 0},
 +              .ob = {3, 3, 3}, /* 3 chain */
 +              .db_stage2 = {3, 3, 3}, /* 3 chain */
 +              .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
 +              .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
 +              .xpaBiasLvl = 0,
 +              .txFrameToDataStart = 0x0e,
 +              .txFrameToPaOn = 0x0e,
 +              .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 +              .antennaGain = 0,
 +              .switchSettling = 0x2d,
 +              .adcDesiredSize = -30,
 +              .txEndToXpaOff = 0,
 +              .txEndToRxOn = 0x2,
 +              .txFrameToXpaOn = 0xe,
 +              .thresh62 = 28,
 +              .papdRateMaskHt20 = LE32(0x0c80c080),
 +              .papdRateMaskHt40 = LE32(0x0080c080),
 +              .futureModal = {
 +                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 +              },
 +       },
 +      .base_ext2 = {
 +              .tempSlopeLow = 0,
 +              .tempSlopeHigh = 0,
 +              .xatten1DBLow = {0, 0, 0},
 +              .xatten1MarginLow = {0, 0, 0},
 +              .xatten1DBHigh = {0, 0, 0},
 +              .xatten1MarginHigh = {0, 0, 0}
 +      },
 +      .calFreqPier5G = {
 +              FREQ2FBIN(5180, 0),
 +              FREQ2FBIN(5220, 0),
 +              FREQ2FBIN(5320, 0),
 +              FREQ2FBIN(5400, 0),
 +              FREQ2FBIN(5500, 0),
 +              FREQ2FBIN(5600, 0),
 +              FREQ2FBIN(5725, 0),
 +              FREQ2FBIN(5825, 0)
 +      },
 +      .calPierData5G = {
 +                      {
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                      },
 +                      {
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                      },
 +                      {
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                      },
 +
 +      },
 +      .calTarget_freqbin_5G = {
 +              FREQ2FBIN(5180, 0),
 +              FREQ2FBIN(5220, 0),
 +              FREQ2FBIN(5320, 0),
 +              FREQ2FBIN(5400, 0),
 +              FREQ2FBIN(5500, 0),
 +              FREQ2FBIN(5600, 0),
 +              FREQ2FBIN(5725, 0),
 +              FREQ2FBIN(5825, 0)
 +      },
 +      .calTarget_freqbin_5GHT20 = {
 +              FREQ2FBIN(5180, 0),
 +              FREQ2FBIN(5240, 0),
 +              FREQ2FBIN(5320, 0),
 +              FREQ2FBIN(5500, 0),
 +              FREQ2FBIN(5700, 0),
 +              FREQ2FBIN(5745, 0),
 +              FREQ2FBIN(5725, 0),
 +              FREQ2FBIN(5825, 0)
 +      },
 +      .calTarget_freqbin_5GHT40 = {
 +              FREQ2FBIN(5180, 0),
 +              FREQ2FBIN(5240, 0),
 +              FREQ2FBIN(5320, 0),
 +              FREQ2FBIN(5500, 0),
 +              FREQ2FBIN(5700, 0),
 +              FREQ2FBIN(5745, 0),
 +              FREQ2FBIN(5725, 0),
 +              FREQ2FBIN(5825, 0)
 +       },
 +      .calTargetPower5G = {
 +              /* 6-24,36,48,54 */
 +              { {20, 20, 20, 10} },
 +              { {20, 20, 20, 10} },
 +              { {20, 20, 20, 10} },
 +              { {20, 20, 20, 10} },
 +              { {20, 20, 20, 10} },
 +              { {20, 20, 20, 10} },
 +              { {20, 20, 20, 10} },
 +              { {20, 20, 20, 10} },
 +       },
 +      .calTargetPower5GHT20 = {
 +              /*
 +               * 0_8_16,1-3_9-11_17-19,
 +               * 4,5,6,7,12,13,14,15,20,21,22,23
 +               */
 +              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 +              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 +              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 +              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 +              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 +              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 +              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 +              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 +       },
 +      .calTargetPower5GHT40 =  {
 +              /*
 +               * 0_8_16,1-3_9-11_17-19,
 +               * 4,5,6,7,12,13,14,15,20,21,22,23
 +               */
 +              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 +              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 +              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 +              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 +              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 +              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 +              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 +              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 +       },
 +      .ctlIndex_5G =  {
 +              0x10, 0x16, 0x18, 0x40, 0x46,
 +              0x48, 0x30, 0x36, 0x38
 +      },
 +      .ctl_freqbin_5G =  {
 +              {
 +                      /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 +                      /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
 +                      /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 +                      /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 +              },
 +              {
 +                      /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 +                      /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
 +                      /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 +                      /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 +              },
 +
 +              {
 +                      /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 +                      /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 +                      /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 +                      /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
 +                      /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
 +                      /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
 +                      /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
 +                      /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
 +              },
 +
 +              {
 +                      /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 +                      /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
 +                      /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[3].ctlEdges[6].bChannel */ 0xFF,
 +                      /* Data[3].ctlEdges[7].bChannel */ 0xFF,
 +              },
 +
 +              {
 +                      /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[4].ctlEdges[4].bChannel */ 0xFF,
 +                      /* Data[4].ctlEdges[5].bChannel */ 0xFF,
 +                      /* Data[4].ctlEdges[6].bChannel */ 0xFF,
 +                      /* Data[4].ctlEdges[7].bChannel */ 0xFF,
 +              },
 +
 +              {
 +                      /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 +                      /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
 +                      /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
 +                      /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 +                      /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
 +                      /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 +                      /* Data[5].ctlEdges[6].bChannel */ 0xFF,
 +                      /* Data[5].ctlEdges[7].bChannel */ 0xFF
 +              },
 +
 +              {
 +                      /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 +                      /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
 +                      /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
 +                      /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
 +              },
 +
 +              {
 +                      /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
 +                      /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
 +                      /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 +                      /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 +              },
 +
 +              {
 +                      /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 +                      /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 +                      /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 +                      /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 +                      /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
 +                      /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 +                      /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
 +                      /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
 +              }
 +       },
 +      .ctlPowerData_5G = {
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 0}, {60, 1}, {60, 0}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
++                              CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 0}, {60, 1}, {60, 1}, {60, 0},
-                               {60, 1}, {60, 0}, {60, 0}, {60, 0},
++                              CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
++                              CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
-                               {60, 0}, {60, 0}, {60, 0}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
++                              CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 0}, {60, 0}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 0}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 0}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 0}, {60, 1},
++                              CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 +                      }
 +              },
 +       }
 +};
 +
 +static const struct ar9300_eeprom ar9300_x113 = {
 +      .eepromVersion = 2,
 +      .templateVersion = 6,
 +      .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
 +      .custData = {"x113-023-f0000"},
 +      .baseEepHeader = {
 +              .regDmn = { LE16(0), LE16(0x1f) },
 +              .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
 +              .opCapFlags = {
 +                      .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
 +                      .eepMisc = 0,
 +              },
 +              .rfSilent = 0,
 +              .blueToothOptions = 0,
 +              .deviceCap = 0,
 +              .deviceType = 5, /* takes lower byte in eeprom location */
 +              .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
 +              .params_for_tuning_caps = {0, 0},
 +              .featureEnable = 0x0d,
 +               /*
 +                * bit0 - enable tx temp comp - disabled
 +                * bit1 - enable tx volt comp - disabled
 +                * bit2 - enable fastClock - enabled
 +                * bit3 - enable doubling - enabled
 +                * bit4 - enable internal regulator - disabled
 +                * bit5 - enable pa predistortion - disabled
 +                */
 +              .miscConfiguration = 0, /* bit0 - turn down drivestrength */
 +              .eepromWriteEnableGpio = 6,
 +              .wlanDisableGpio = 0,
 +              .wlanLedGpio = 8,
 +              .rxBandSelectGpio = 0xff,
 +              .txrxgain = 0x21,
 +              .swreg = 0,
 +       },
 +      .modalHeader2G = {
 +      /* ar9300_modal_eep_header  2g */
 +              /* 4 idle,t1,t2,b(4 bits per setting) */
 +              .antCtrlCommon = LE32(0x110),
 +              /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 +              .antCtrlCommon2 = LE32(0x44444),
 +
 +              /*
 +               * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
 +               * rx1, rx12, b (2 bits each)
 +               */
 +              .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
 +
 +              /*
 +               * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
 +               * for ar9280 (0xa20c/b20c 5:0)
 +               */
 +              .xatten1DB = {0, 0, 0},
 +
 +              /*
 +               * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 +               * for ar9280 (0xa20c/b20c 16:12
 +               */
 +              .xatten1Margin = {0, 0, 0},
 +              .tempSlope = 25,
 +              .voltSlope = 0,
 +
 +              /*
 +               * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 +               * channels in usual fbin coding format
 +               */
 +              .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
 +
 +              /*
 +               * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 +               * if the register is per chain
 +               */
 +              .noiseFloorThreshCh = {-1, 0, 0},
 +              .ob = {1, 1, 1},/* 3 chain */
 +              .db_stage2 = {1, 1, 1}, /* 3 chain  */
 +              .db_stage3 = {0, 0, 0},
 +              .db_stage4 = {0, 0, 0},
 +              .xpaBiasLvl = 0,
 +              .txFrameToDataStart = 0x0e,
 +              .txFrameToPaOn = 0x0e,
 +              .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 +              .antennaGain = 0,
 +              .switchSettling = 0x2c,
 +              .adcDesiredSize = -30,
 +              .txEndToXpaOff = 0,
 +              .txEndToRxOn = 0x2,
 +              .txFrameToXpaOn = 0xe,
 +              .thresh62 = 28,
 +              .papdRateMaskHt20 = LE32(0x0c80c080),
 +              .papdRateMaskHt40 = LE32(0x0080c080),
 +              .futureModal = {
 +                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 +              },
 +       },
 +       .base_ext1 = {
 +              .ant_div_control = 0,
 +              .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 +       },
 +      .calFreqPier2G = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2437, 1),
 +              FREQ2FBIN(2472, 1),
 +       },
 +      /* ar9300_cal_data_per_freq_op_loop 2g */
 +      .calPierData2G = {
 +              { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 +              { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 +              { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 +       },
 +      .calTarget_freqbin_Cck = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2472, 1),
 +       },
 +      .calTarget_freqbin_2G = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2437, 1),
 +              FREQ2FBIN(2472, 1)
 +       },
 +      .calTarget_freqbin_2GHT20 = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2437, 1),
 +              FREQ2FBIN(2472, 1)
 +       },
 +      .calTarget_freqbin_2GHT40 = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2437, 1),
 +              FREQ2FBIN(2472, 1)
 +       },
 +      .calTargetPowerCck = {
 +               /* 1L-5L,5S,11L,11S */
 +               { {34, 34, 34, 34} },
 +               { {34, 34, 34, 34} },
 +      },
 +      .calTargetPower2G = {
 +               /* 6-24,36,48,54 */
 +               { {34, 34, 32, 32} },
 +               { {34, 34, 32, 32} },
 +               { {34, 34, 32, 32} },
 +      },
 +      .calTargetPower2GHT20 = {
 +              { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 +              { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 +              { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 +      },
 +      .calTargetPower2GHT40 = {
 +              { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 +              { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 +              { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 +      },
 +      .ctlIndex_2G =  {
 +              0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 +              0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 +      },
 +      .ctl_freqbin_2G = {
 +              {
 +                      FREQ2FBIN(2412, 1),
 +                      FREQ2FBIN(2417, 1),
 +                      FREQ2FBIN(2457, 1),
 +                      FREQ2FBIN(2462, 1)
 +              },
 +              {
 +                      FREQ2FBIN(2412, 1),
 +                      FREQ2FBIN(2417, 1),
 +                      FREQ2FBIN(2462, 1),
 +                      0xFF,
 +              },
 +
 +              {
 +                      FREQ2FBIN(2412, 1),
 +                      FREQ2FBIN(2417, 1),
 +                      FREQ2FBIN(2462, 1),
 +                      0xFF,
 +              },
 +              {
 +                      FREQ2FBIN(2422, 1),
 +                      FREQ2FBIN(2427, 1),
 +                      FREQ2FBIN(2447, 1),
 +                      FREQ2FBIN(2452, 1)
 +              },
 +
 +              {
 +                      /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 +                      /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 +              },
 +
 +              {
 +                      /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 +                      0,
 +              },
 +
 +              {
 +                      /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 +                      FREQ2FBIN(2472, 1),
 +                      0,
 +              },
 +
 +              {
 +                      /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 +                      /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 +                      /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 +                      /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 +              },
 +
 +              {
 +                      /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 +              },
 +
 +              {
 +                      /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 +                      0
 +              },
 +
 +              {
 +                      /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 +                      0
 +              },
 +
 +              {
 +                      /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 +                      /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 +                      /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 +                      /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 +              }
 +       },
 +      .ctlPowerData_2G = {
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++               { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 +
-                { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++               { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 +
-                { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 +
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
-                { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
++               { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 +       },
 +      .modalHeader5G = {
 +              /* 4 idle,t1,t2,b (4 bits per setting) */
 +              .antCtrlCommon = LE32(0x220),
 +              /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 +              .antCtrlCommon2 = LE32(0x11111),
 +               /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 +              .antCtrlChain = {
 +                      LE16(0x150), LE16(0x150), LE16(0x150),
 +              },
 +               /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 +              .xatten1DB = {0, 0, 0},
 +
 +              /*
 +               * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 +               * for merlin (0xa20c/b20c 16:12
 +               */
 +              .xatten1Margin = {0, 0, 0},
 +              .tempSlope = 68,
 +              .voltSlope = 0,
 +              /* spurChans spur channels in usual fbin coding format */
 +              .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
 +              /* noiseFloorThreshCh Check if the register is per chain */
 +              .noiseFloorThreshCh = {-1, 0, 0},
 +              .ob = {3, 3, 3}, /* 3 chain */
 +              .db_stage2 = {3, 3, 3}, /* 3 chain */
 +              .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
 +              .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
 +              .xpaBiasLvl = 0,
 +              .txFrameToDataStart = 0x0e,
 +              .txFrameToPaOn = 0x0e,
 +              .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 +              .antennaGain = 0,
 +              .switchSettling = 0x2d,
 +              .adcDesiredSize = -30,
 +              .txEndToXpaOff = 0,
 +              .txEndToRxOn = 0x2,
 +              .txFrameToXpaOn = 0xe,
 +              .thresh62 = 28,
 +              .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 +              .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 +              .futureModal = {
 +                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 +              },
 +       },
 +      .base_ext2 = {
 +              .tempSlopeLow = 72,
 +              .tempSlopeHigh = 105,
 +              .xatten1DBLow = {0, 0, 0},
 +              .xatten1MarginLow = {0, 0, 0},
 +              .xatten1DBHigh = {0, 0, 0},
 +              .xatten1MarginHigh = {0, 0, 0}
 +       },
 +      .calFreqPier5G = {
 +              FREQ2FBIN(5180, 0),
 +              FREQ2FBIN(5240, 0),
 +              FREQ2FBIN(5320, 0),
 +              FREQ2FBIN(5400, 0),
 +              FREQ2FBIN(5500, 0),
 +              FREQ2FBIN(5600, 0),
 +              FREQ2FBIN(5745, 0),
 +              FREQ2FBIN(5785, 0)
 +      },
 +      .calPierData5G = {
 +                      {
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                      },
 +                      {
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                      },
 +                      {
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                              {0, 0, 0, 0, 0},
 +                      },
 +
 +      },
 +      .calTarget_freqbin_5G = {
 +              FREQ2FBIN(5180, 0),
 +              FREQ2FBIN(5220, 0),
 +              FREQ2FBIN(5320, 0),
 +              FREQ2FBIN(5400, 0),
 +              FREQ2FBIN(5500, 0),
 +              FREQ2FBIN(5600, 0),
 +              FREQ2FBIN(5745, 0),
 +              FREQ2FBIN(5785, 0)
 +      },
 +      .calTarget_freqbin_5GHT20 = {
 +              FREQ2FBIN(5180, 0),
 +              FREQ2FBIN(5240, 0),
 +              FREQ2FBIN(5320, 0),
 +              FREQ2FBIN(5400, 0),
 +              FREQ2FBIN(5500, 0),
 +              FREQ2FBIN(5700, 0),
 +              FREQ2FBIN(5745, 0),
 +              FREQ2FBIN(5825, 0)
 +      },
 +      .calTarget_freqbin_5GHT40 = {
 +              FREQ2FBIN(5190, 0),
 +              FREQ2FBIN(5230, 0),
 +              FREQ2FBIN(5320, 0),
 +              FREQ2FBIN(5410, 0),
 +              FREQ2FBIN(5510, 0),
 +              FREQ2FBIN(5670, 0),
 +              FREQ2FBIN(5755, 0),
 +              FREQ2FBIN(5825, 0)
 +       },
 +      .calTargetPower5G = {
 +              /* 6-24,36,48,54 */
 +              { {42, 40, 40, 34} },
 +              { {42, 40, 40, 34} },
 +              { {42, 40, 40, 34} },
 +              { {42, 40, 40, 34} },
 +              { {42, 40, 40, 34} },
 +              { {42, 40, 40, 34} },
 +              { {42, 40, 40, 34} },
 +              { {42, 40, 40, 34} },
 +       },
 +      .calTargetPower5GHT20 = {
 +              /*
 +               * 0_8_16,1-3_9-11_17-19,
 +               * 4,5,6,7,12,13,14,15,20,21,22,23
 +               */
 +              { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
 +              { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
 +              { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
 +              { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
 +              { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
 +              { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
 +              { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
 +              { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
 +       },
 +      .calTargetPower5GHT40 =  {
 +              /*
 +               * 0_8_16,1-3_9-11_17-19,
 +               * 4,5,6,7,12,13,14,15,20,21,22,23
 +               */
 +              { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
 +              { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
 +              { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
 +              { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
 +              { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
 +              { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
 +              { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
 +              { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
 +       },
 +      .ctlIndex_5G =  {
 +              0x10, 0x16, 0x18, 0x40, 0x46,
 +              0x48, 0x30, 0x36, 0x38
 +      },
 +      .ctl_freqbin_5G =  {
 +              {
 +                      /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 +                      /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
 +                      /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 +                      /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 +              },
 +              {
 +                      /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 +                      /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
 +                      /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 +                      /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 +              },
 +
 +              {
 +                      /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 +                      /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 +                      /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 +                      /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
 +                      /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
 +                      /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
 +                      /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
 +                      /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
 +              },
 +
 +              {
 +                      /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 +                      /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
 +                      /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[3].ctlEdges[6].bChannel */ 0xFF,
 +                      /* Data[3].ctlEdges[7].bChannel */ 0xFF,
 +              },
 +
 +              {
 +                      /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[4].ctlEdges[4].bChannel */ 0xFF,
 +                      /* Data[4].ctlEdges[5].bChannel */ 0xFF,
 +                      /* Data[4].ctlEdges[6].bChannel */ 0xFF,
 +                      /* Data[4].ctlEdges[7].bChannel */ 0xFF,
 +              },
 +
 +              {
 +                      /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 +                      /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
 +                      /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
 +                      /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 +                      /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
 +                      /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 +                      /* Data[5].ctlEdges[6].bChannel */ 0xFF,
 +                      /* Data[5].ctlEdges[7].bChannel */ 0xFF
 +              },
 +
 +              {
 +                      /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 +                      /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
 +                      /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
 +                      /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
 +              },
 +
 +              {
 +                      /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
 +                      /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
 +                      /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 +                      /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 +              },
 +
 +              {
 +                      /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 +                      /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 +                      /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 +                      /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 +                      /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
 +                      /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 +                      /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
 +                      /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
 +              }
 +       },
 +      .ctlPowerData_5G = {
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 0}, {60, 1}, {60, 0}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
++                              CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 0}, {60, 1}, {60, 1}, {60, 0},
-                               {60, 1}, {60, 0}, {60, 0}, {60, 0},
++                              CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
++                              CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
-                               {60, 0}, {60, 0}, {60, 0}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
++                              CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 0}, {60, 0}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 0}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 0}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 0}, {60, 1},
++                              CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 +                      }
 +              },
 +       }
 +};
 +
 +
 +static const struct ar9300_eeprom ar9300_h112 = {
 +      .eepromVersion = 2,
 +      .templateVersion = 3,
 +      .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
 +      .custData = {"h112-241-f0000"},
 +      .baseEepHeader = {
 +              .regDmn = { LE16(0), LE16(0x1f) },
 +              .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
 +              .opCapFlags = {
 +                      .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
 +                      .eepMisc = 0,
 +              },
 +              .rfSilent = 0,
 +              .blueToothOptions = 0,
 +              .deviceCap = 0,
 +              .deviceType = 5, /* takes lower byte in eeprom location */
 +              .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
 +              .params_for_tuning_caps = {0, 0},
 +              .featureEnable = 0x0d,
 +              /*
 +               * bit0 - enable tx temp comp - disabled
 +               * bit1 - enable tx volt comp - disabled
 +               * bit2 - enable fastClock - enabled
 +               * bit3 - enable doubling - enabled
 +               * bit4 - enable internal regulator - disabled
 +               * bit5 - enable pa predistortion - disabled
 +               */
 +              .miscConfiguration = 0, /* bit0 - turn down drivestrength */
 +              .eepromWriteEnableGpio = 6,
 +              .wlanDisableGpio = 0,
 +              .wlanLedGpio = 8,
 +              .rxBandSelectGpio = 0xff,
 +              .txrxgain = 0x10,
 +              .swreg = 0,
 +      },
 +      .modalHeader2G = {
 +              /* ar9300_modal_eep_header  2g */
 +              /* 4 idle,t1,t2,b(4 bits per setting) */
 +              .antCtrlCommon = LE32(0x110),
 +              /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 +              .antCtrlCommon2 = LE32(0x44444),
 +
 +              /*
 +               * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
 +               * rx1, rx12, b (2 bits each)
 +               */
 +              .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
 +
 +              /*
 +               * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
 +               * for ar9280 (0xa20c/b20c 5:0)
 +               */
 +              .xatten1DB = {0, 0, 0},
 +
 +              /*
 +               * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 +               * for ar9280 (0xa20c/b20c 16:12
 +               */
 +              .xatten1Margin = {0, 0, 0},
 +              .tempSlope = 25,
 +              .voltSlope = 0,
 +
 +              /*
 +               * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 +               * channels in usual fbin coding format
 +               */
 +              .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
 +
 +              /*
 +               * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 +               * if the register is per chain
 +               */
 +              .noiseFloorThreshCh = {-1, 0, 0},
 +              .ob = {1, 1, 1},/* 3 chain */
 +              .db_stage2 = {1, 1, 1}, /* 3 chain  */
 +              .db_stage3 = {0, 0, 0},
 +              .db_stage4 = {0, 0, 0},
 +              .xpaBiasLvl = 0,
 +              .txFrameToDataStart = 0x0e,
 +              .txFrameToPaOn = 0x0e,
 +              .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 +              .antennaGain = 0,
 +              .switchSettling = 0x2c,
 +              .adcDesiredSize = -30,
 +              .txEndToXpaOff = 0,
 +              .txEndToRxOn = 0x2,
 +              .txFrameToXpaOn = 0xe,
 +              .thresh62 = 28,
 +              .papdRateMaskHt20 = LE32(0x80c080),
 +              .papdRateMaskHt40 = LE32(0x80c080),
 +              .futureModal = {
 +                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 +              },
 +      },
 +      .base_ext1 = {
 +              .ant_div_control = 0,
 +              .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 +      },
 +      .calFreqPier2G = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2437, 1),
 +              FREQ2FBIN(2472, 1),
 +      },
 +      /* ar9300_cal_data_per_freq_op_loop 2g */
 +      .calPierData2G = {
 +              { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 +              { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 +              { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 +      },
 +      .calTarget_freqbin_Cck = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2484, 1),
 +      },
 +      .calTarget_freqbin_2G = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2437, 1),
 +              FREQ2FBIN(2472, 1)
 +      },
 +      .calTarget_freqbin_2GHT20 = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2437, 1),
 +              FREQ2FBIN(2472, 1)
 +      },
 +      .calTarget_freqbin_2GHT40 = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2437, 1),
 +              FREQ2FBIN(2472, 1)
 +      },
 +      .calTargetPowerCck = {
 +              /* 1L-5L,5S,11L,11S */
 +              { {34, 34, 34, 34} },
 +              { {34, 34, 34, 34} },
 +      },
 +      .calTargetPower2G = {
 +              /* 6-24,36,48,54 */
 +              { {34, 34, 32, 32} },
 +              { {34, 34, 32, 32} },
 +              { {34, 34, 32, 32} },
 +      },
 +      .calTargetPower2GHT20 = {
 +              { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
 +              { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
 +              { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
 +      },
 +      .calTargetPower2GHT40 = {
 +              { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
 +              { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
 +              { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
 +      },
 +      .ctlIndex_2G =  {
 +              0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 +              0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 +      },
 +      .ctl_freqbin_2G = {
 +              {
 +                      FREQ2FBIN(2412, 1),
 +                      FREQ2FBIN(2417, 1),
 +                      FREQ2FBIN(2457, 1),
 +                      FREQ2FBIN(2462, 1)
 +              },
 +              {
 +                      FREQ2FBIN(2412, 1),
 +                      FREQ2FBIN(2417, 1),
 +                      FREQ2FBIN(2462, 1),
 +                      0xFF,
 +              },
 +
 +              {
 +                      FREQ2FBIN(2412, 1),
 +                      FREQ2FBIN(2417, 1),
 +                      FREQ2FBIN(2462, 1),
 +                      0xFF,
 +              },
 +              {
 +                      FREQ2FBIN(2422, 1),
 +                      FREQ2FBIN(2427, 1),
 +                      FREQ2FBIN(2447, 1),
 +                      FREQ2FBIN(2452, 1)
 +              },
 +
 +              {
 +                      /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 +                      /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 +              },
 +
 +              {
 +                      /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 +                      0,
 +              },
 +
 +              {
 +                      /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 +                      FREQ2FBIN(2472, 1),
 +                      0,
 +              },
 +
 +              {
 +                      /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 +                      /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 +                      /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 +                      /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 +              },
 +
 +              {
 +                      /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 +              },
 +
 +              {
 +                      /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 +                      0
 +              },
 +
 +              {
 +                      /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 +                      0
 +              },
 +
 +              {
 +                      /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 +                      /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 +                      /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 +                      /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 +              }
 +      },
 +      .ctlPowerData_2G = {
-               { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-               { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-               { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++              { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 +
-               { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
-               { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-               { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++              { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 +
-               { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
-               { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-               { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 +
-               { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-               { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
-               { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 +      },
 +      .modalHeader5G = {
 +              /* 4 idle,t1,t2,b (4 bits per setting) */
 +              .antCtrlCommon = LE32(0x220),
 +              /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 +              .antCtrlCommon2 = LE32(0x44444),
 +              /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 +              .antCtrlChain = {
 +                      LE16(0x150), LE16(0x150), LE16(0x150),
 +              },
 +              /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 +              .xatten1DB = {0, 0, 0},
 +
 +              /*
 +               * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 +               * for merlin (0xa20c/b20c 16:12
 +               */
 +              .xatten1Margin = {0, 0, 0},
 +              .tempSlope = 45,
 +              .voltSlope = 0,
 +              /* spurChans spur channels in usual fbin coding format */
 +              .spurChans = {0, 0, 0, 0, 0},
 +              /* noiseFloorThreshCh Check if the register is per chain */
 +              .noiseFloorThreshCh = {-1, 0, 0},
 +              .ob = {3, 3, 3}, /* 3 chain */
 +              .db_stage2 = {3, 3, 3}, /* 3 chain */
 +              .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
 +              .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
 +              .xpaBiasLvl = 0,
 +              .txFrameToDataStart = 0x0e,
 +              .txFrameToPaOn = 0x0e,
 +              .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 +              .antennaGain = 0,
 +              .switchSettling = 0x2d,
 +              .adcDesiredSize = -30,
 +              .txEndToXpaOff = 0,
 +              .txEndToRxOn = 0x2,
 +              .txFrameToXpaOn = 0xe,
 +              .thresh62 = 28,
 +              .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 +              .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 +              .futureModal = {
 +                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 +              },
 +      },
 +      .base_ext2 = {
 +              .tempSlopeLow = 40,
 +              .tempSlopeHigh = 50,
 +              .xatten1DBLow = {0, 0, 0},
 +              .xatten1MarginLow = {0, 0, 0},
 +              .xatten1DBHigh = {0, 0, 0},
 +              .xatten1MarginHigh = {0, 0, 0}
 +      },
 +      .calFreqPier5G = {
 +              FREQ2FBIN(5180, 0),
 +              FREQ2FBIN(5220, 0),
 +              FREQ2FBIN(5320, 0),
 +              FREQ2FBIN(5400, 0),
 +              FREQ2FBIN(5500, 0),
 +              FREQ2FBIN(5600, 0),
 +              FREQ2FBIN(5700, 0),
 +              FREQ2FBIN(5825, 0)
 +      },
 +      .calPierData5G = {
 +              {
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +              },
 +              {
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +              },
 +              {
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +              },
 +
 +      },
 +      .calTarget_freqbin_5G = {
 +              FREQ2FBIN(5180, 0),
 +              FREQ2FBIN(5240, 0),
 +              FREQ2FBIN(5320, 0),
 +              FREQ2FBIN(5400, 0),
 +              FREQ2FBIN(5500, 0),
 +              FREQ2FBIN(5600, 0),
 +              FREQ2FBIN(5700, 0),
 +              FREQ2FBIN(5825, 0)
 +      },
 +      .calTarget_freqbin_5GHT20 = {
 +              FREQ2FBIN(5180, 0),
 +              FREQ2FBIN(5240, 0),
 +              FREQ2FBIN(5320, 0),
 +              FREQ2FBIN(5400, 0),
 +              FREQ2FBIN(5500, 0),
 +              FREQ2FBIN(5700, 0),
 +              FREQ2FBIN(5745, 0),
 +              FREQ2FBIN(5825, 0)
 +      },
 +      .calTarget_freqbin_5GHT40 = {
 +              FREQ2FBIN(5180, 0),
 +              FREQ2FBIN(5240, 0),
 +              FREQ2FBIN(5320, 0),
 +              FREQ2FBIN(5400, 0),
 +              FREQ2FBIN(5500, 0),
 +              FREQ2FBIN(5700, 0),
 +              FREQ2FBIN(5745, 0),
 +              FREQ2FBIN(5825, 0)
 +      },
 +      .calTargetPower5G = {
 +              /* 6-24,36,48,54 */
 +              { {30, 30, 28, 24} },
 +              { {30, 30, 28, 24} },
 +              { {30, 30, 28, 24} },
 +              { {30, 30, 28, 24} },
 +              { {30, 30, 28, 24} },
 +              { {30, 30, 28, 24} },
 +              { {30, 30, 28, 24} },
 +              { {30, 30, 28, 24} },
 +      },
 +      .calTargetPower5GHT20 = {
 +              /*
 +               * 0_8_16,1-3_9-11_17-19,
 +               * 4,5,6,7,12,13,14,15,20,21,22,23
 +               */
 +              { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
 +              { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
 +              { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
 +              { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
 +              { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
 +              { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
 +              { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
 +              { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
 +      },
 +      .calTargetPower5GHT40 =  {
 +              /*
 +               * 0_8_16,1-3_9-11_17-19,
 +               * 4,5,6,7,12,13,14,15,20,21,22,23
 +               */
 +              { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
 +              { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
 +              { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
 +              { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
 +              { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
 +              { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
 +              { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
 +              { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
 +      },
 +      .ctlIndex_5G =  {
 +              0x10, 0x16, 0x18, 0x40, 0x46,
 +              0x48, 0x30, 0x36, 0x38
 +      },
 +      .ctl_freqbin_5G =  {
 +              {
 +                      /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 +                      /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
 +                      /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 +                      /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 +              },
 +              {
 +                      /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 +                      /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
 +                      /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 +                      /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 +              },
 +
 +              {
 +                      /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 +                      /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 +                      /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 +                      /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
 +                      /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
 +                      /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
 +                      /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
 +                      /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
 +              },
 +
 +              {
 +                      /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 +                      /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
 +                      /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[3].ctlEdges[6].bChannel */ 0xFF,
 +                      /* Data[3].ctlEdges[7].bChannel */ 0xFF,
 +              },
 +
 +              {
 +                      /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[4].ctlEdges[4].bChannel */ 0xFF,
 +                      /* Data[4].ctlEdges[5].bChannel */ 0xFF,
 +                      /* Data[4].ctlEdges[6].bChannel */ 0xFF,
 +                      /* Data[4].ctlEdges[7].bChannel */ 0xFF,
 +              },
 +
 +              {
 +                      /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 +                      /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
 +                      /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
 +                      /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 +                      /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
 +                      /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 +                      /* Data[5].ctlEdges[6].bChannel */ 0xFF,
 +                      /* Data[5].ctlEdges[7].bChannel */ 0xFF
 +              },
 +
 +              {
 +                      /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 +                      /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
 +                      /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
 +                      /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
 +              },
 +
 +              {
 +                      /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
 +                      /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
 +                      /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 +                      /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 +              },
 +
 +              {
 +                      /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 +                      /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 +                      /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 +                      /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 +                      /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
 +                      /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 +                      /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
 +                      /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
 +              }
 +      },
 +      .ctlPowerData_5G = {
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 0}, {60, 1}, {60, 0}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
++                              CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 0}, {60, 1}, {60, 1}, {60, 0},
-                               {60, 1}, {60, 0}, {60, 0}, {60, 0},
++                              CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
++                              CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
-                               {60, 0}, {60, 0}, {60, 0}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
++                              CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 0}, {60, 0}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 0}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 0}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 0}, {60, 1},
++                              CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 +                      }
 +              },
 +      }
 +};
 +
 +
 +static const struct ar9300_eeprom ar9300_x112 = {
 +      .eepromVersion = 2,
 +      .templateVersion = 5,
 +      .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
 +      .custData = {"x112-041-f0000"},
 +      .baseEepHeader = {
 +              .regDmn = { LE16(0), LE16(0x1f) },
 +              .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
 +              .opCapFlags = {
 +                      .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
 +                      .eepMisc = 0,
 +              },
 +              .rfSilent = 0,
 +              .blueToothOptions = 0,
 +              .deviceCap = 0,
 +              .deviceType = 5, /* takes lower byte in eeprom location */
 +              .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
 +              .params_for_tuning_caps = {0, 0},
 +              .featureEnable = 0x0d,
 +              /*
 +               * bit0 - enable tx temp comp - disabled
 +               * bit1 - enable tx volt comp - disabled
 +               * bit2 - enable fastclock - enabled
 +               * bit3 - enable doubling - enabled
 +               * bit4 - enable internal regulator - disabled
 +               * bit5 - enable pa predistortion - disabled
 +               */
 +              .miscConfiguration = 0, /* bit0 - turn down drivestrength */
 +              .eepromWriteEnableGpio = 6,
 +              .wlanDisableGpio = 0,
 +              .wlanLedGpio = 8,
 +              .rxBandSelectGpio = 0xff,
 +              .txrxgain = 0x0,
 +              .swreg = 0,
 +      },
 +      .modalHeader2G = {
 +              /* ar9300_modal_eep_header  2g */
 +              /* 4 idle,t1,t2,b(4 bits per setting) */
 +              .antCtrlCommon = LE32(0x110),
 +              /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 +              .antCtrlCommon2 = LE32(0x22222),
 +
 +              /*
 +               * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
 +               * rx1, rx12, b (2 bits each)
 +               */
 +              .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
 +
 +              /*
 +               * xatten1DB[AR9300_max_chains];  3 xatten1_db
 +               * for ar9280 (0xa20c/b20c 5:0)
 +               */
 +              .xatten1DB = {0x1b, 0x1b, 0x1b},
 +
 +              /*
 +               * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
 +               * for ar9280 (0xa20c/b20c 16:12
 +               */
 +              .xatten1Margin = {0x15, 0x15, 0x15},
 +              .tempSlope = 50,
 +              .voltSlope = 0,
 +
 +              /*
 +               * spurChans[OSPrey_eeprom_modal_sPURS]; spur
 +               * channels in usual fbin coding format
 +               */
 +              .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
 +
 +              /*
 +               * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
 +               * if the register is per chain
 +               */
 +              .noiseFloorThreshCh = {-1, 0, 0},
 +              .ob = {1, 1, 1},/* 3 chain */
 +              .db_stage2 = {1, 1, 1}, /* 3 chain  */
 +              .db_stage3 = {0, 0, 0},
 +              .db_stage4 = {0, 0, 0},
 +              .xpaBiasLvl = 0,
 +              .txFrameToDataStart = 0x0e,
 +              .txFrameToPaOn = 0x0e,
 +              .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 +              .antennaGain = 0,
 +              .switchSettling = 0x2c,
 +              .adcDesiredSize = -30,
 +              .txEndToXpaOff = 0,
 +              .txEndToRxOn = 0x2,
 +              .txFrameToXpaOn = 0xe,
 +              .thresh62 = 28,
 +              .papdRateMaskHt20 = LE32(0x0c80c080),
 +              .papdRateMaskHt40 = LE32(0x0080c080),
 +              .futureModal = {
 +                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 +              },
 +      },
 +      .base_ext1 = {
 +              .ant_div_control = 0,
 +              .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 +      },
 +      .calFreqPier2G = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2437, 1),
 +              FREQ2FBIN(2472, 1),
 +      },
 +      /* ar9300_cal_data_per_freq_op_loop 2g */
 +      .calPierData2G = {
 +              { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 +              { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 +              { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 +      },
 +      .calTarget_freqbin_Cck = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2472, 1),
 +      },
 +      .calTarget_freqbin_2G = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2437, 1),
 +              FREQ2FBIN(2472, 1)
 +      },
 +      .calTarget_freqbin_2GHT20 = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2437, 1),
 +              FREQ2FBIN(2472, 1)
 +      },
 +      .calTarget_freqbin_2GHT40 = {
 +              FREQ2FBIN(2412, 1),
 +              FREQ2FBIN(2437, 1),
 +              FREQ2FBIN(2472, 1)
 +      },
 +      .calTargetPowerCck = {
 +              /* 1L-5L,5S,11L,11s */
 +              { {38, 38, 38, 38} },
 +              { {38, 38, 38, 38} },
 +      },
 +      .calTargetPower2G = {
 +              /* 6-24,36,48,54 */
 +              { {38, 38, 36, 34} },
 +              { {38, 38, 36, 34} },
 +              { {38, 38, 34, 32} },
 +      },
 +      .calTargetPower2GHT20 = {
 +              { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
 +              { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
 +              { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
 +      },
 +      .calTargetPower2GHT40 = {
 +              { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
 +              { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
 +              { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
 +      },
 +      .ctlIndex_2G =  {
 +              0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 +              0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 +      },
 +      .ctl_freqbin_2G = {
 +              {
 +                      FREQ2FBIN(2412, 1),
 +                      FREQ2FBIN(2417, 1),
 +                      FREQ2FBIN(2457, 1),
 +                      FREQ2FBIN(2462, 1)
 +              },
 +              {
 +                      FREQ2FBIN(2412, 1),
 +                      FREQ2FBIN(2417, 1),
 +                      FREQ2FBIN(2462, 1),
 +                      0xFF,
 +              },
 +
 +              {
 +                      FREQ2FBIN(2412, 1),
 +                      FREQ2FBIN(2417, 1),
 +                      FREQ2FBIN(2462, 1),
 +                      0xFF,
 +              },
 +              {
 +                      FREQ2FBIN(2422, 1),
 +                      FREQ2FBIN(2427, 1),
 +                      FREQ2FBIN(2447, 1),
 +                      FREQ2FBIN(2452, 1)
 +              },
 +
 +              {
 +                      /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
 +                      /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
 +              },
 +
 +              {
 +                      /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
 +                      0,
 +              },
 +
 +              {
 +                      /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
 +                      FREQ2FBIN(2472, 1),
 +                      0,
 +              },
 +
 +              {
 +                      /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
 +                      /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
 +                      /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
 +                      /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
 +              },
 +
 +              {
 +                      /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
 +              },
 +
 +              {
 +                      /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
 +                      0
 +              },
 +
 +              {
 +                      /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
 +                      /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
 +                      /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
 +                      0
 +              },
 +
 +              {
 +                      /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
 +                      /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
 +                      /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
 +                      /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
 +              }
 +      },
 +      .ctlPowerData_2G = {
-               { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-               { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-               { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++              { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 +
-               { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
-               { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-               { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++              { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 +
-               { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
-               { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-               { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 +
-               { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-               { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
-               { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
++              { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 +      },
 +      .modalHeader5G = {
 +              /* 4 idle,t1,t2,b (4 bits per setting) */
 +              .antCtrlCommon = LE32(0x110),
 +              /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 +              .antCtrlCommon2 = LE32(0x22222),
 +              /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 +              .antCtrlChain = {
 +                      LE16(0x0), LE16(0x0), LE16(0x0),
 +              },
 +              /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
 +              .xatten1DB = {0x13, 0x19, 0x17},
 +
 +              /*
 +               * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
 +               * for merlin (0xa20c/b20c 16:12
 +               */
 +              .xatten1Margin = {0x19, 0x19, 0x19},
 +              .tempSlope = 70,
 +              .voltSlope = 15,
 +              /* spurChans spur channels in usual fbin coding format */
 +              .spurChans = {0, 0, 0, 0, 0},
 +              /* noiseFloorThreshch check if the register is per chain */
 +              .noiseFloorThreshCh = {-1, 0, 0},
 +              .ob = {3, 3, 3}, /* 3 chain */
 +              .db_stage2 = {3, 3, 3}, /* 3 chain */
 +              .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
 +              .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
 +              .xpaBiasLvl = 0,
 +              .txFrameToDataStart = 0x0e,
 +              .txFrameToPaOn = 0x0e,
 +              .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 +              .antennaGain = 0,
 +              .switchSettling = 0x2d,
 +              .adcDesiredSize = -30,
 +              .txEndToXpaOff = 0,
 +              .txEndToRxOn = 0x2,
 +              .txFrameToXpaOn = 0xe,
 +              .thresh62 = 28,
 +              .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 +              .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 +              .futureModal = {
 +                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 +              },
 +      },
 +      .base_ext2 = {
 +              .tempSlopeLow = 72,
 +              .tempSlopeHigh = 105,
 +              .xatten1DBLow = {0x10, 0x14, 0x10},
 +              .xatten1MarginLow = {0x19, 0x19 , 0x19},
 +              .xatten1DBHigh = {0x1d, 0x20, 0x24},
 +              .xatten1MarginHigh = {0x10, 0x10, 0x10}
 +      },
 +      .calFreqPier5G = {
 +              FREQ2FBIN(5180, 0),
 +              FREQ2FBIN(5220, 0),
 +              FREQ2FBIN(5320, 0),
 +              FREQ2FBIN(5400, 0),
 +              FREQ2FBIN(5500, 0),
 +              FREQ2FBIN(5600, 0),
 +              FREQ2FBIN(5700, 0),
 +              FREQ2FBIN(5785, 0)
 +      },
 +      .calPierData5G = {
 +              {
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +              },
 +              {
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +              },
 +              {
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +                      {0, 0, 0, 0, 0},
 +              },
 +
 +      },
 +      .calTarget_freqbin_5G = {
 +              FREQ2FBIN(5180, 0),
 +              FREQ2FBIN(5220, 0),
 +              FREQ2FBIN(5320, 0),
 +              FREQ2FBIN(5400, 0),
 +              FREQ2FBIN(5500, 0),
 +              FREQ2FBIN(5600, 0),
 +              FREQ2FBIN(5725, 0),
 +              FREQ2FBIN(5825, 0)
 +      },
 +      .calTarget_freqbin_5GHT20 = {
 +              FREQ2FBIN(5180, 0),
 +              FREQ2FBIN(5220, 0),
 +              FREQ2FBIN(5320, 0),
 +              FREQ2FBIN(5400, 0),
 +              FREQ2FBIN(5500, 0),
 +              FREQ2FBIN(5600, 0),
 +              FREQ2FBIN(5725, 0),
 +              FREQ2FBIN(5825, 0)
 +      },
 +      .calTarget_freqbin_5GHT40 = {
 +              FREQ2FBIN(5180, 0),
 +              FREQ2FBIN(5220, 0),
 +              FREQ2FBIN(5320, 0),
 +              FREQ2FBIN(5400, 0),
 +              FREQ2FBIN(5500, 0),
 +              FREQ2FBIN(5600, 0),
 +              FREQ2FBIN(5725, 0),
 +              FREQ2FBIN(5825, 0)
 +      },
 +      .calTargetPower5G = {
 +              /* 6-24,36,48,54 */
 +              { {32, 32, 28, 26} },
 +              { {32, 32, 28, 26} },
 +              { {32, 32, 28, 26} },
 +              { {32, 32, 26, 24} },
 +              { {32, 32, 26, 24} },
 +              { {32, 32, 24, 22} },
 +              { {30, 30, 24, 22} },
 +              { {30, 30, 24, 22} },
 +      },
 +      .calTargetPower5GHT20 = {
 +              /*
 +               * 0_8_16,1-3_9-11_17-19,
 +               * 4,5,6,7,12,13,14,15,20,21,22,23
 +               */
 +              { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
 +              { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
 +              { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
 +              { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
 +              { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
 +              { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
 +              { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
 +              { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
 +      },
 +      .calTargetPower5GHT40 =  {
 +              /*
 +               * 0_8_16,1-3_9-11_17-19,
 +               * 4,5,6,7,12,13,14,15,20,21,22,23
 +               */
 +              { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
 +              { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
 +              { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
 +              { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
 +              { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
 +              { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
 +              { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
 +              { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
 +      },
 +      .ctlIndex_5G =  {
 +              0x10, 0x16, 0x18, 0x40, 0x46,
 +              0x48, 0x30, 0x36, 0x38
 +      },
 +      .ctl_freqbin_5G =  {
 +              {
 +                      /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
 +                      /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
 +                      /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
 +                      /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
 +              },
 +              {
 +                      /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
 +                      /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
 +                      /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
 +                      /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
 +              },
 +
 +              {
 +                      /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
 +                      /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
 +                      /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
 +                      /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
 +                      /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
 +                      /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
 +                      /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
 +                      /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
 +              },
 +
 +              {
 +                      /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
 +                      /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
 +                      /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[3].ctledges[6].bchannel */ 0xFF,
 +                      /* Data[3].ctledges[7].bchannel */ 0xFF,
 +              },
 +
 +              {
 +                      /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[4].ctledges[4].bchannel */ 0xFF,
 +                      /* Data[4].ctledges[5].bchannel */ 0xFF,
 +                      /* Data[4].ctledges[6].bchannel */ 0xFF,
 +                      /* Data[4].ctledges[7].bchannel */ 0xFF,
 +              },
 +
 +              {
 +                      /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
 +                      /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
 +                      /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
 +                      /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
 +                      /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
 +                      /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
 +                      /* Data[5].ctledges[6].bchannel */ 0xFF,
 +                      /* Data[5].ctledges[7].bchannel */ 0xFF
 +              },
 +
 +              {
 +                      /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
 +                      /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
 +                      /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
 +                      /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
 +              },
 +
 +              {
 +                      /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
 +                      /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
 +                      /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
 +                      /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
 +                      /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
 +                      /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
 +                      /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
 +                      /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
 +              },
 +
 +              {
 +                      /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
 +                      /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
 +                      /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
 +                      /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
 +                      /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
 +                      /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
 +                      /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
 +                      /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
 +              }
 +      },
 +      .ctlPowerData_5G = {
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 0}, {60, 1}, {60, 0}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
++                              CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 0}, {60, 1}, {60, 1}, {60, 0},
-                               {60, 1}, {60, 0}, {60, 0}, {60, 0},
++                              CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
++                              CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
-                               {60, 0}, {60, 0}, {60, 0}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
++                              CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 0}, {60, 0}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 1}, {60, 0}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
++                              CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 +                      }
 +              },
 +              {
 +                      {
-                               {60, 1}, {60, 0}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 0}, {60, 1},
++                              CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
++                              CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 +                      }
 +              },
 +      }
 +};
 +
 +static const struct ar9300_eeprom ar9300_h116 = {
 +      .eepromVersion = 2,
 +      .templateVersion = 4,
 +      .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
 +      .custData = {"h116-041-f0000"},
        .baseEepHeader = {
                .regDmn = { LE16(0), LE16(0x1f) },
 -              .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
 +              .txrxMask =  0x33, /* 4 bits tx and 4 bits rx */
                .opCapFlags = {
                        .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
                        .eepMisc = 0,
                .deviceType = 5, /* takes lower byte in eeprom location */
                .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
                .params_for_tuning_caps = {0, 0},
 -              .featureEnable = 0x0c,
 +              .featureEnable = 0x0d,
                 /*
                  * bit0 - enable tx temp comp - disabled
                  * bit1 - enable tx volt comp - disabled
                  * bit5 - enable pa predistortion - disabled
                  */
                .miscConfiguration = 0, /* bit0 - turn down drivestrength */
 -              .eepromWriteEnableGpio = 3,
 +              .eepromWriteEnableGpio = 6,
                .wlanDisableGpio = 0,
                .wlanLedGpio = 8,
                .rxBandSelectGpio = 0xff,
 -              .txrxgain = 0,
 +              .txrxgain = 0x10,
                .swreg = 0,
         },
        .modalHeader2G = {
                /* 4 idle,t1,t2,b(4 bits per setting) */
                .antCtrlCommon = LE32(0x110),
                /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 -              .antCtrlCommon2 = LE32(0x22222),
 +              .antCtrlCommon2 = LE32(0x44444),
  
                /*
                 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
                 * rx1, rx12, b (2 bits each)
                 */
 -              .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
 +              .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
  
                /*
                 * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
                 * for ar9280 (0xa20c/b20c 5:0)
                 */
 -              .xatten1DB = {0, 0, 0},
 +              .xatten1DB = {0x1f, 0x1f, 0x1f},
  
                /*
                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
                 * for ar9280 (0xa20c/b20c 16:12
                 */
 -              .xatten1Margin = {0, 0, 0},
 -              .tempSlope = 36,
 +              .xatten1Margin = {0x12, 0x12, 0x12},
 +              .tempSlope = 25,
                .voltSlope = 0,
  
                /*
                 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
                 * channels in usual fbin coding format
                 */
 -              .spurChans = {0, 0, 0, 0, 0},
 +              .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
  
                /*
                 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
                .txEndToRxOn = 0x2,
                .txFrameToXpaOn = 0xe,
                .thresh62 = 28,
 -              .papdRateMaskHt20 = LE32(0x80c080),
 -              .papdRateMaskHt40 = LE32(0x80c080),
 +              .papdRateMaskHt20 = LE32(0x0c80C080),
 +              .papdRateMaskHt40 = LE32(0x0080C080),
                .futureModal = {
 -                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 -                      0, 0, 0, 0, 0, 0, 0, 0
 +                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                },
         },
 +       .base_ext1 = {
 +              .ant_div_control = 0,
 +              .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 +       },
        .calFreqPier2G = {
                FREQ2FBIN(2412, 1),
                FREQ2FBIN(2437, 1),
         },
        .calTarget_freqbin_Cck = {
                FREQ2FBIN(2412, 1),
 -              FREQ2FBIN(2484, 1),
 +              FREQ2FBIN(2472, 1),
         },
        .calTarget_freqbin_2G = {
                FREQ2FBIN(2412, 1),
         },
        .calTargetPowerCck = {
                 /* 1L-5L,5S,11L,11S */
 -               { {36, 36, 36, 36} },
 -               { {36, 36, 36, 36} },
 +               { {34, 34, 34, 34} },
 +               { {34, 34, 34, 34} },
        },
        .calTargetPower2G = {
                 /* 6-24,36,48,54 */
 -               { {32, 32, 28, 24} },
 -               { {32, 32, 28, 24} },
 -               { {32, 32, 28, 24} },
 +               { {34, 34, 32, 32} },
 +               { {34, 34, 32, 32} },
 +               { {34, 34, 32, 32} },
        },
        .calTargetPower2GHT20 = {
 -              { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 -              { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 -              { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 +              { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
 +              { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
 +              { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
        },
        .calTargetPower2GHT40 = {
 -              { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 -              { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 -              { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 +              { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 +              { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 +              { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
        },
        .ctlIndex_2G =  {
                0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
                        /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
                        /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
                        /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 -                      /* Data[11].ctlEdges[3].bChannel */
 -                      FREQ2FBIN(2462, 1),
 +                      /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
                }
         },
        .ctlPowerData_2G = {
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
  
-                { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
+                { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  
-                { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  
-                { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
-                { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
-                { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
         },
        .modalHeader5G = {
                /* 4 idle,t1,t2,b (4 bits per setting) */
 -              .antCtrlCommon = LE32(0x110),
 +              .antCtrlCommon = LE32(0x220),
                /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 -              .antCtrlCommon2 = LE32(0x22222),
 +              .antCtrlCommon2 = LE32(0x44444),
                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
                .antCtrlChain = {
 -                      LE16(0x000), LE16(0x000), LE16(0x000),
 +                      LE16(0x150), LE16(0x150), LE16(0x150),
                },
                 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 -              .xatten1DB = {0, 0, 0},
 +              .xatten1DB = {0x19, 0x19, 0x19},
  
                /*
                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
                 * for merlin (0xa20c/b20c 16:12
                 */
 -              .xatten1Margin = {0, 0, 0},
 -              .tempSlope = 68,
 +              .xatten1Margin = {0x14, 0x14, 0x14},
 +              .tempSlope = 70,
                .voltSlope = 0,
                /* spurChans spur channels in usual fbin coding format */
                .spurChans = {0, 0, 0, 0, 0},
                .txEndToRxOn = 0x2,
                .txFrameToXpaOn = 0xe,
                .thresh62 = 28,
 -              .papdRateMaskHt20 = LE32(0xf0e0e0),
 -              .papdRateMaskHt40 = LE32(0xf0e0e0),
 +              .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 +              .papdRateMaskHt40 = LE32(0x6cf0e0e0),
                .futureModal = {
 -                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 -                      0, 0, 0, 0, 0, 0, 0, 0
 +                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                },
         },
 +      .base_ext2 = {
 +              .tempSlopeLow = 35,
 +              .tempSlopeHigh = 50,
 +              .xatten1DBLow = {0, 0, 0},
 +              .xatten1MarginLow = {0, 0, 0},
 +              .xatten1DBHigh = {0, 0, 0},
 +              .xatten1MarginHigh = {0, 0, 0}
 +       },
        .calFreqPier5G = {
                FREQ2FBIN(5180, 0),
                FREQ2FBIN(5220, 0),
                FREQ2FBIN(5400, 0),
                FREQ2FBIN(5500, 0),
                FREQ2FBIN(5600, 0),
 -              FREQ2FBIN(5725, 0),
 -              FREQ2FBIN(5825, 0)
 +              FREQ2FBIN(5700, 0),
 +              FREQ2FBIN(5785, 0)
        },
        .calPierData5G = {
                        {
        },
        .calTarget_freqbin_5G = {
                FREQ2FBIN(5180, 0),
 -              FREQ2FBIN(5220, 0),
 +              FREQ2FBIN(5240, 0),
                FREQ2FBIN(5320, 0),
                FREQ2FBIN(5400, 0),
                FREQ2FBIN(5500, 0),
                FREQ2FBIN(5600, 0),
 -              FREQ2FBIN(5725, 0),
 +              FREQ2FBIN(5700, 0),
                FREQ2FBIN(5825, 0)
        },
        .calTarget_freqbin_5GHT20 = {
                FREQ2FBIN(5180, 0),
                FREQ2FBIN(5240, 0),
                FREQ2FBIN(5320, 0),
 +              FREQ2FBIN(5400, 0),
                FREQ2FBIN(5500, 0),
                FREQ2FBIN(5700, 0),
                FREQ2FBIN(5745, 0),
 -              FREQ2FBIN(5725, 0),
                FREQ2FBIN(5825, 0)
        },
        .calTarget_freqbin_5GHT40 = {
                FREQ2FBIN(5180, 0),
                FREQ2FBIN(5240, 0),
                FREQ2FBIN(5320, 0),
 +              FREQ2FBIN(5400, 0),
                FREQ2FBIN(5500, 0),
                FREQ2FBIN(5700, 0),
                FREQ2FBIN(5745, 0),
 -              FREQ2FBIN(5725, 0),
                FREQ2FBIN(5825, 0)
         },
        .calTargetPower5G = {
                /* 6-24,36,48,54 */
 -              { {20, 20, 20, 10} },
 -              { {20, 20, 20, 10} },
 -              { {20, 20, 20, 10} },
 -              { {20, 20, 20, 10} },
 -              { {20, 20, 20, 10} },
 -              { {20, 20, 20, 10} },
 -              { {20, 20, 20, 10} },
 -              { {20, 20, 20, 10} },
 +              { {30, 30, 28, 24} },
 +              { {30, 30, 28, 24} },
 +              { {30, 30, 28, 24} },
 +              { {30, 30, 28, 24} },
 +              { {30, 30, 28, 24} },
 +              { {30, 30, 28, 24} },
 +              { {30, 30, 28, 24} },
 +              { {30, 30, 28, 24} },
         },
        .calTargetPower5GHT20 = {
                /*
                 * 0_8_16,1-3_9-11_17-19,
                 * 4,5,6,7,12,13,14,15,20,21,22,23
                 */
 -              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 -              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 -              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 -              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 -              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 -              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 -              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 -              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 +              { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
 +              { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
 +              { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
 +              { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
 +              { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
 +              { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
 +              { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
 +              { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
         },
        .calTargetPower5GHT40 =  {
                /*
                 * 0_8_16,1-3_9-11_17-19,
                 * 4,5,6,7,12,13,14,15,20,21,22,23
                 */
 -              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 -              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 -              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 -              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 -              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 -              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 -              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 -              { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 +              { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
 +              { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
 +              { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
 +              { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
 +              { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
 +              { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
 +              { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
 +              { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
         },
        .ctlIndex_5G =  {
                0x10, 0x16, 0x18, 0x40, 0x46,
        .ctlPowerData_5G = {
                {
                        {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
+                               CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                               CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
                        }
                },
                {
                        {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
+                               CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                               CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
                        }
                },
                {
                        {
-                               {60, 0}, {60, 1}, {60, 0}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
+                               CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                               CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
                        }
                },
                {
                        {
-                               {60, 0}, {60, 1}, {60, 1}, {60, 0},
-                               {60, 1}, {60, 0}, {60, 0}, {60, 0},
+                               CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                               CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
                        }
                },
                {
                        {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
-                               {60, 0}, {60, 0}, {60, 0}, {60, 0},
+                               CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                               CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
                        }
                },
                {
                        {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 0}, {60, 0}, {60, 0},
+                               CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                               CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
                        }
                },
                {
                        {
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 1},
+                               CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                               CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
                        }
                },
                {
                        {
-                               {60, 1}, {60, 1}, {60, 0}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 1}, {60, 0},
+                               CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                               CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
                        }
                },
                {
                        {
-                               {60, 1}, {60, 0}, {60, 1}, {60, 1},
-                               {60, 1}, {60, 1}, {60, 0}, {60, 1},
+                               CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
+                               CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
                        }
                },
         }
  };
  
 +
 +static const struct ar9300_eeprom *ar9300_eep_templates[] = {
 +      &ar9300_default,
 +      &ar9300_x112,
 +      &ar9300_h116,
 +      &ar9300_h112,
 +      &ar9300_x113,
 +};
 +
 +static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
 +{
 +#define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
 +      int it;
 +
 +      for (it = 0; it < N_LOOP; it++)
 +              if (ar9300_eep_templates[it]->templateVersion == id)
 +                      return ar9300_eep_templates[it];
 +      return NULL;
 +#undef N_LOOP
 +}
 +
 +
  static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
  {
        if (fbin == AR9300_BCHAN_UNUSED)
@@@ -2982,16 -639,6 +2985,16 @@@ static int ath9k_hw_ar9300_check_eeprom
        return 0;
  }
  
 +static int interpolate(int x, int xa, int xb, int ya, int yb)
 +{
 +      int bf, factor, plus;
 +
 +      bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
 +      factor = bf / 2;
 +      plus = bf % 2;
 +      return ya + factor + plus;
 +}
 +
  static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
                                      enum eeprom_param param)
  {
                return le32_to_cpu(pBase->swreg);
        case EEP_PAPRD:
                return !!(pBase->featureEnable & BIT(5));
 +      case EEP_CHAIN_MASK_REDUCE:
 +              return (pBase->miscConfiguration >> 0x3) & 0x1;
        default:
                return 0;
        }
@@@ -3106,36 -751,6 +3109,36 @@@ error
        return false;
  }
  
 +static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
 +{
 +      REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
 +
 +      if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
 +                         AR9300_OTP_STATUS_VALID, 1000))
 +              return false;
 +
 +      *data = REG_READ(ah, AR9300_OTP_READ_DATA);
 +      return true;
 +}
 +
 +static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
 +                          int count)
 +{
 +      u32 data;
 +      int i;
 +
 +      for (i = 0; i < count; i++) {
 +              int offset = 8 * ((address - i) % 4);
 +              if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
 +                      return false;
 +
 +              buffer[i] = (data >> offset) & 0xff;
 +      }
 +
 +      return true;
 +}
 +
 +
  static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
                                   int *length, int *major, int *minor)
  {
@@@ -3212,7 -827,6 +3215,7 @@@ static int ar9300_compress_decision(str
  {
        struct ath_common *common = ath9k_hw_common(ah);
        u8 *dptr;
 +      const struct ar9300_eeprom *eep = NULL;
  
        switch (code) {
        case _CompressNone:
                if (reference == 0) {
                        dptr = mptr;
                } else {
 -                      if (reference != 2) {
 +                      eep = ar9003_eeprom_struct_find_by_id(reference);
 +                      if (eep == NULL) {
                                ath_print(common, ATH_DBG_EEPROM,
                                          "cant find reference eeprom"
                                          "struct %d\n", reference);
                                return -1;
                        }
 -                      memcpy(mptr, &ar9300_default, mdata_size);
 +                      memcpy(mptr, eep, mdata_size);
                }
                ath_print(common, ATH_DBG_EEPROM,
                          "restore eeprom %d: block, reference %d,"
        return 0;
  }
  
 +typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
 +                             int count);
 +
 +static bool ar9300_check_header(void *data)
 +{
 +      u32 *word = data;
 +      return !(*word == 0 || *word == ~0);
 +}
 +
 +static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
 +                                     int base_addr)
 +{
 +      u8 header[4];
 +
 +      if (!read(ah, base_addr, header, 4))
 +              return false;
 +
 +      return ar9300_check_header(header);
 +}
 +
 +static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
 +                                     int mdata_size)
 +{
 +      struct ath_common *common = ath9k_hw_common(ah);
 +      u16 *data = (u16 *) mptr;
 +      int i;
 +
 +      for (i = 0; i < mdata_size / 2; i++, data++)
 +              ath9k_hw_nvram_read(common, i, data);
 +
 +      return 0;
 +}
  /*
   * Read the configuration data from the eeprom.
   * The data can be put in any specified memory buffer.
@@@ -3305,10 -886,6 +3308,10 @@@ static int ar9300_eeprom_restore_intern
        int it;
        u16 checksum, mchecksum;
        struct ath_common *common = ath9k_hw_common(ah);
 +      eeprom_read_op read;
 +
 +      if (ath9k_hw_use_flash(ah))
 +              return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
  
        word = kzalloc(2048, GFP_KERNEL);
        if (!word)
  
        memcpy(mptr, &ar9300_default, mdata_size);
  
 +      read = ar9300_read_eeprom;
 +      cptr = AR9300_BASE_ADDR;
 +      ath_print(common, ATH_DBG_EEPROM,
 +              "Trying EEPROM accesss at Address 0x%04x\n", cptr);
 +      if (ar9300_check_eeprom_header(ah, read, cptr))
 +              goto found;
 +
 +      cptr = AR9300_BASE_ADDR_512;
 +      ath_print(common, ATH_DBG_EEPROM,
 +              "Trying EEPROM accesss at Address 0x%04x\n", cptr);
 +      if (ar9300_check_eeprom_header(ah, read, cptr))
 +              goto found;
 +
 +      read = ar9300_read_otp;
        cptr = AR9300_BASE_ADDR;
 +      ath_print(common, ATH_DBG_EEPROM,
 +              "Trying OTP accesss at Address 0x%04x\n", cptr);
 +      if (ar9300_check_eeprom_header(ah, read, cptr))
 +              goto found;
 +
 +      cptr = AR9300_BASE_ADDR_512;
 +      ath_print(common, ATH_DBG_EEPROM,
 +              "Trying OTP accesss at Address 0x%04x\n", cptr);
 +      if (ar9300_check_eeprom_header(ah, read, cptr))
 +              goto found;
 +
 +      goto fail;
 +
 +found:
 +      ath_print(common, ATH_DBG_EEPROM, "Found valid EEPROM data");
 +
        for (it = 0; it < MSTATE; it++) {
 -              if (!ar9300_read_eeprom(ah, cptr, word, COMP_HDR_LEN))
 +              if (!read(ah, cptr, word, COMP_HDR_LEN))
                        goto fail;
  
 -              if ((word[0] == 0 && word[1] == 0 && word[2] == 0 &&
 -                   word[3] == 0) || (word[0] == 0xff && word[1] == 0xff
 -                                     && word[2] == 0xff && word[3] == 0xff))
 +              if (!ar9300_check_header(word))
                        break;
  
                ar9300_comp_hdr_unpack(word, &code, &reference,
                }
  
                osize = length;
 -              ar9300_read_eeprom(ah, cptr, word,
 -                                 COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
 +              read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
                checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
                mchecksum = word[COMP_HDR_LEN + osize] |
                    (word[COMP_HDR_LEN + osize + 1] << 8);
@@@ -3445,9 -995,9 +3448,9 @@@ static s32 ar9003_hw_xpa_bias_level_get
  static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
  {
        int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
 -      REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, (bias & 0x3));
 -      REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_SPARE,
 -                    ((bias >> 2) & 0x3));
 +      REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
 +      REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB, bias >> 2);
 +      REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
  }
  
  static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
@@@ -3550,82 -1100,6 +3553,82 @@@ static void ar9003_hw_drive_strength_ap
        REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
  }
  
 +static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
 +                                   struct ath9k_channel *chan)
 +{
 +      int f[3], t[3];
 +      u16 value;
 +      struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 +
 +      if (chain >= 0 && chain < 3) {
 +              if (IS_CHAN_2GHZ(chan))
 +                      return eep->modalHeader2G.xatten1DB[chain];
 +              else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
 +                      t[0] = eep->base_ext2.xatten1DBLow[chain];
 +                      f[0] = 5180;
 +                      t[1] = eep->modalHeader5G.xatten1DB[chain];
 +                      f[1] = 5500;
 +                      t[2] = eep->base_ext2.xatten1DBHigh[chain];
 +                      f[2] = 5785;
 +                      value = ar9003_hw_power_interpolate((s32) chan->channel,
 +                                                          f, t, 3);
 +                      return value;
 +              } else
 +                      return eep->modalHeader5G.xatten1DB[chain];
 +      }
 +
 +      return 0;
 +}
 +
 +
 +static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
 +                                          struct ath9k_channel *chan)
 +{
 +      int f[3], t[3];
 +      u16 value;
 +      struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 +
 +      if (chain >= 0 && chain < 3) {
 +              if (IS_CHAN_2GHZ(chan))
 +                      return eep->modalHeader2G.xatten1Margin[chain];
 +              else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
 +                      t[0] = eep->base_ext2.xatten1MarginLow[chain];
 +                      f[0] = 5180;
 +                      t[1] = eep->modalHeader5G.xatten1Margin[chain];
 +                      f[1] = 5500;
 +                      t[2] = eep->base_ext2.xatten1MarginHigh[chain];
 +                      f[2] = 5785;
 +                      value = ar9003_hw_power_interpolate((s32) chan->channel,
 +                                                          f, t, 3);
 +                      return value;
 +              } else
 +                      return eep->modalHeader5G.xatten1Margin[chain];
 +      }
 +
 +      return 0;
 +}
 +
 +static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
 +{
 +      int i;
 +      u16 value;
 +      unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
 +                                        AR_PHY_EXT_ATTEN_CTL_1,
 +                                        AR_PHY_EXT_ATTEN_CTL_2,
 +                                       };
 +
 +      /* Test value. if 0 then attenuation is unused. Don't load anything. */
 +      for (i = 0; i < 3; i++) {
 +              value = ar9003_hw_atten_chain_get(ah, i, chan);
 +              REG_RMW_FIELD(ah, ext_atten_reg[i],
 +                            AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
 +
 +              value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
 +              REG_RMW_FIELD(ah, ext_atten_reg[i],
 +                            AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, value);
 +      }
 +}
 +
  static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
  {
        int internal_regulator =
@@@ -3657,7 -1131,6 +3660,7 @@@ static void ath9k_hw_ar9300_set_board_v
        ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
        ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
        ar9003_hw_drive_strength_apply(ah);
 +      ar9003_hw_atten_apply(ah, chan);
        ar9003_hw_internal_regulator_apply(ah);
  }
  
@@@ -3719,7 -1192,7 +3722,7 @@@ static int ar9003_hw_power_interpolate(
                        if (hx == lx)
                                y = ly;
                        else    /* interpolate  */
 -                              y = ly + (((x - lx) * (hy - ly)) / (hx - lx));
 +                              y = interpolate(x, lx, hx, ly, hy);
                } else          /* only low is good, use it */
                        y = ly;
        } else if (hhave)       /* only high is good, use it */
@@@ -4167,7 -1640,6 +4170,7 @@@ static int ar9003_hw_power_control_over
  {
        int tempSlope = 0;
        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 +      int f[3], t[3];
  
        REG_RMW(ah, AR_PHY_TPC_11_B0,
                (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
         */
        if (frequency < 4000)
                tempSlope = eep->modalHeader2G.tempSlope;
 -      else
 +      else if (eep->base_ext2.tempSlopeLow != 0) {
 +              t[0] = eep->base_ext2.tempSlopeLow;
 +              f[0] = 5180;
 +              t[1] = eep->modalHeader5G.tempSlope;
 +              f[1] = 5500;
 +              t[2] = eep->base_ext2.tempSlopeHigh;
 +              f[2] = 5785;
 +              tempSlope = ar9003_hw_power_interpolate((s32) frequency,
 +                                                      f, t, 3);
 +      } else
                tempSlope = eep->modalHeader5G.tempSlope;
  
        REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
@@@ -4309,23 -1772,25 +4312,23 @@@ static int ar9003_hw_calibration_apply(
                        /* so is the high frequency, interpolate */
                        if (hfrequency[ichain] - frequency < 1000) {
  
 -                              correction[ichain] = lcorrection[ichain] +
 -                                  (((frequency - lfrequency[ichain]) *
 -                                    (hcorrection[ichain] -
 -                                     lcorrection[ichain])) /
 -                                   (hfrequency[ichain] - lfrequency[ichain]));
 -
 -                              temperature[ichain] = ltemperature[ichain] +
 -                                  (((frequency - lfrequency[ichain]) *
 -                                    (htemperature[ichain] -
 -                                     ltemperature[ichain])) /
 -                                   (hfrequency[ichain] - lfrequency[ichain]));
 -
 -                              voltage[ichain] =
 -                                  lvoltage[ichain] +
 -                                  (((frequency -
 -                                     lfrequency[ichain]) * (hvoltage[ichain] -
 -                                                            lvoltage[ichain]))
 -                                   / (hfrequency[ichain] -
 -                                      lfrequency[ichain]));
 +                              correction[ichain] = interpolate(frequency,
 +                                              lfrequency[ichain],
 +                                              hfrequency[ichain],
 +                                              lcorrection[ichain],
 +                                              hcorrection[ichain]);
 +
 +                              temperature[ichain] = interpolate(frequency,
 +                                              lfrequency[ichain],
 +                                              hfrequency[ichain],
 +                                              ltemperature[ichain],
 +                                              htemperature[ichain]);
 +
 +                              voltage[ichain] = interpolate(frequency,
 +                                              lfrequency[ichain],
 +                                              hfrequency[ichain],
 +                                              lvoltage[ichain],
 +                                              hvoltage[ichain]);
                        }
                        /* only low is good, use it */
                        else {
@@@ -4365,9 -1830,9 +4368,9 @@@ static u16 ar9003_hw_get_direct_edge_po
        struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
  
        if (is2GHz)
-               return ctl_2g[idx].ctlEdges[edge].tPower;
+               return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
        else
-               return ctl_5g[idx].ctlEdges[edge].tPower;
+               return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
  }
  
  static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
  
        if (is2GHz) {
                if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
-                   ctl_2g[idx].ctlEdges[edge - 1].flag)
-                       return ctl_2g[idx].ctlEdges[edge - 1].tPower;
+                   CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
+                       return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
        } else {
                if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
-                   ctl_5g[idx].ctlEdges[edge - 1].flag)
-                       return ctl_5g[idx].ctlEdges[edge - 1].tPower;
+                   CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
+                       return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
        }
  
        return AR9300_MAX_RATE_POWER;
@@@ -4457,16 -1922,14 +4460,16 @@@ static void ar9003_hw_set_power_per_rat
        int i;
        int16_t  twiceLargestAntenna;
        u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
 -      u16 ctlModesFor11a[] = {
 +      static const u16 ctlModesFor11a[] = {
                CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
        };
 -      u16 ctlModesFor11g[] = {
 +      static const u16 ctlModesFor11g[] = {
                CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
                CTL_11G_EXT, CTL_2GHT40
        };
 -      u16 numCtlModes, *pCtlMode, ctlMode, freq;
 +      u16 numCtlModes;
 +      const u16 *pCtlMode;
 +      u16 ctlMode, freq;
        struct chan_centers centers;
        u8 *ctlIndex;
        u8 ctlNum;
@@@ -4671,9 -2134,8 +4674,9 @@@ static void ath9k_hw_ar9300_set_txpower
                                        struct ath9k_channel *chan, u16 cfgCtl,
                                        u8 twiceAntennaReduction,
                                        u8 twiceMaxRegulatoryPower,
 -                                      u8 powerLimit)
 +                                      u8 powerLimit, bool test)
  {
 +      struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
        struct ath_common *common = ath9k_hw_common(ah);
        u8 targetPowerValT2[ar9300RateSize];
        unsigned int i = 0;
                                           twiceMaxRegulatoryPower,
                                           powerLimit);
  
 -      while (i < ar9300RateSize) {
 +      regulatory->max_power_level = 0;
 +      for (i = 0; i < ar9300RateSize; i++) {
 +              if (targetPowerValT2[i] > regulatory->max_power_level)
 +                      regulatory->max_power_level = targetPowerValT2[i];
 +      }
 +
 +      if (test)
 +              return;
 +
 +      for (i = 0; i < ar9300RateSize; i++) {
                ath_print(common, ATH_DBG_EEPROM,
                          "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
                i++;
                i++;
        }
  
 -      /* Write target power array to registers */
 -      ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
 -
        /*
         * This is the TX power we send back to driver core,
         * and it can use to pass to userspace to display our
                i = ALL_TARGET_HT20_0_8_16; /* ht20 */
  
        ah->txpower_limit = targetPowerValT2[i];
 +      regulatory->max_power_level = targetPowerValT2[i];
  
 +      /* Write target power array to registers */
 +      ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
        ar9003_hw_calibration_apply(ah, chan->channel);
  }
  
index 57f64dbbcd8993eafc16e7dc732da9899cb5f1a1,655b3033396c7f89ce1585479afb918102f993ae..9c1463307f0c94a4dffbd99f418eadcf859d71f1
  #define FIXED_CCA_THRESHOLD 15
  
  #define AR9300_BASE_ADDR 0x3ff
 +#define AR9300_BASE_ADDR_512 0x1ff
 +
 +#define AR9300_OTP_BASE                       0x14000
 +#define AR9300_OTP_STATUS             0x15f18
 +#define AR9300_OTP_STATUS_TYPE                0x7
 +#define AR9300_OTP_STATUS_VALID               0x4
 +#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
 +#define AR9300_OTP_STATUS_SM_BUSY     0x1
 +#define AR9300_OTP_READ_DATA          0x15f1c
  
  enum targetPowerHTRates {
        HT_TARGET_RATE_0_8_16,
@@@ -245,7 -236,7 +245,7 @@@ struct ar9300_modal_eep_header 
        u8 thresh62;
        __le32 papdRateMaskHt20;
        __le32 papdRateMaskHt40;
 -      u8 futureModal[24];
 +      u8 futureModal[10];
  } __packed;
  
  struct ar9300_cal_data_per_freq_op_loop {
@@@ -270,33 -261,14 +270,28 @@@ struct cal_tgt_pow_ht 
        u8 tPow2x[14];
  } __packed;
  
- struct cal_ctl_edge_pwr {
-       u8 tPower:6,
-          flag:2;
- } __packed;
  struct cal_ctl_data_2g {
-       struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_2G];
+       u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];
  } __packed;
  
  struct cal_ctl_data_5g {
-       struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
+       u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
  } __packed;
  
 +struct ar9300_BaseExtension_1 {
 +      u8 ant_div_control;
 +      u8 future[13];
 +} __packed;
 +
 +struct ar9300_BaseExtension_2 {
 +      int8_t    tempSlopeLow;
 +      int8_t    tempSlopeHigh;
 +      u8   xatten1DBLow[AR9300_MAX_CHAINS];
 +      u8   xatten1MarginLow[AR9300_MAX_CHAINS];
 +      u8   xatten1DBHigh[AR9300_MAX_CHAINS];
 +      u8   xatten1MarginHigh[AR9300_MAX_CHAINS];
 +} __packed;
 +
  struct ar9300_eeprom {
        u8 eepromVersion;
        u8 templateVersion;
        struct ar9300_base_eep_hdr baseEepHeader;
  
        struct ar9300_modal_eep_header modalHeader2G;
 +      struct ar9300_BaseExtension_1 base_ext1;
        u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
        struct ar9300_cal_data_per_freq_op_loop
         calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
        u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
        struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
        struct ar9300_modal_eep_header modalHeader5G;
 +      struct ar9300_BaseExtension_2 base_ext2;
        u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
        struct ar9300_cal_data_per_freq_op_loop
         calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
index efba413561a44b7e87ac8e40043e899fea469a41,0d0bec3628ececb4fa29663dbffb3fdb9d20b3bb..4210a9306955f500674985357655c52ee7674637
@@@ -21,6 -21,7 +21,7 @@@
  #include <linux/device.h>
  #include <linux/leds.h>
  #include <linux/completion.h>
+ #include <linux/pm_qos_params.h>
  
  #include "debug.h"
  #include "common.h"
@@@ -86,19 -87,33 +87,19 @@@ struct ath_config 
  /**
   * enum buffer_type - Buffer type flags
   *
 - * @BUF_HT: Send this buffer using HT capabilities
   * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
   * @BUF_AGGR: Indicates whether the buffer can be aggregated
   *    (used in aggregation scheduling)
 - * @BUF_RETRY: Indicates whether the buffer is retried
   * @BUF_XRETRY: To denote excessive retries of the buffer
   */
  enum buffer_type {
 -      BUF_HT                  = BIT(1),
        BUF_AMPDU               = BIT(2),
        BUF_AGGR                = BIT(3),
 -      BUF_RETRY               = BIT(4),
        BUF_XRETRY              = BIT(5),
  };
  
 -#define bf_nframes            bf_state.bfs_nframes
 -#define bf_al                 bf_state.bfs_al
 -#define bf_frmlen             bf_state.bfs_frmlen
 -#define bf_retries            bf_state.bfs_retries
 -#define bf_seqno              bf_state.bfs_seqno
 -#define bf_tidno              bf_state.bfs_tidno
 -#define bf_keyix                bf_state.bfs_keyix
 -#define bf_keytype            bf_state.bfs_keytype
 -#define bf_isht(bf)           (bf->bf_state.bf_type & BUF_HT)
  #define bf_isampdu(bf)                (bf->bf_state.bf_type & BUF_AMPDU)
  #define bf_isaggr(bf)         (bf->bf_state.bf_type & BUF_AGGR)
 -#define bf_isretried(bf)      (bf->bf_state.bf_type & BUF_RETRY)
  #define bf_isxretried(bf)     (bf->bf_state.bf_type & BUF_XRETRY)
  
  #define ATH_TXSTATUS_RING_SIZE 64
@@@ -163,8 -178,8 +164,8 @@@ void ath_descdma_cleanup(struct ath_sof
  
  /* returns delimiter padding required given the packet length */
  #define ATH_AGGR_GET_NDELIM(_len)                                     \
 -      (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ?           \
 -        (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
 +       (((_len) >= ATH_AGGR_MINPLEN) ? 0 :                             \
 +        DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
  
  #define BAW_WITHIN(_start, _bawsz, _seqno) \
        ((((_seqno) - (_start)) & 4095) < (_bawsz))
@@@ -181,6 -196,7 +182,6 @@@ enum ATH_AGGR_STATUS 
  
  #define ATH_TXFIFO_DEPTH 8
  struct ath_txq {
 -      int axq_class;
        u32 axq_qnum;
        u32 *axq_link;
        struct list_head axq_q;
        struct list_head txq_fifo_pending;
        u8 txq_headidx;
        u8 txq_tailidx;
 +      int pending_frames;
  };
  
  struct ath_atx_ac {
 +      struct ath_txq *txq;
        int sched;
 -      int qnum;
        struct list_head list;
        struct list_head tid_q;
  };
  
 +struct ath_frame_info {
 +      int framelen;
 +      u32 keyix;
 +      enum ath9k_key_type keytype;
 +      u8 retries;
 +      u16 seqno;
 +};
 +
  struct ath_buf_state {
 -      int bfs_nframes;
 -      u16 bfs_al;
 -      u16 bfs_frmlen;
 -      int bfs_seqno;
 -      int bfs_tidno;
 -      int bfs_retries;
        u8 bf_type;
        u8 bfs_paprd;
 -      unsigned long bfs_paprd_timestamp;
 -      u32 bfs_keyix;
 -      enum ath9k_key_type bfs_keytype;
 +      enum ath9k_internal_frame_type bfs_ftype;
  };
  
  struct ath_buf {
        dma_addr_t bf_daddr;            /* physical addr of desc */
        dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
        bool bf_stale;
 -      bool bf_tx_aborted;
        u16 bf_flags;
        struct ath_buf_state bf_state;
        struct ath_wiphy *aphy;
@@@ -255,6 -271,7 +256,6 @@@ struct ath_node 
        struct ath_atx_ac ac[WME_NUM_AC];
        u16 maxampdu;
        u8 mpdudensity;
 -      int last_rssi;
  };
  
  #define AGGR_CLEANUP         BIT(1)
  
  struct ath_tx_control {
        struct ath_txq *txq;
 +      struct ath_node *an;
        int if_id;
        enum ath9k_internal_frame_type frame_type;
        u8 paprd;
  struct ath_tx {
        u16 seq_no;
        u32 txqsetup;
 -      int hwq_map[WME_NUM_AC];
        spinlock_t txbuflock;
        struct list_head txbuf;
        struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
        struct ath_descdma txdma;
 -      int pending_frames[WME_NUM_AC];
 +      struct ath_txq *txq_map[WME_NUM_AC];
  };
  
  struct ath_rx_edma {
@@@ -294,6 -311,7 +295,6 @@@ struct ath_rx 
        u8 rxotherant;
        u32 *rxlink;
        unsigned int rxfilter;
 -      spinlock_t pcu_lock;
        spinlock_t rxbuflock;
        struct list_head rxbuf;
        struct ath_descdma rxdma;
@@@ -310,6 -328,7 +311,6 @@@ void ath_rx_cleanup(struct ath_softc *s
  int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
  struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
  void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 -int ath_tx_setup(struct ath_softc *sc, int haltype);
  void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
  void ath_draintxq(struct ath_softc *sc,
                     struct ath_txq *txq, bool retry_tx);
@@@ -324,6 -343,7 +325,6 @@@ int ath_tx_start(struct ieee80211_hw *h
                 struct ath_tx_control *txctl);
  void ath_tx_tasklet(struct ath_softc *sc);
  void ath_tx_edma_tasklet(struct ath_softc *sc);
 -void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
  int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
                      u16 tid, u16 *ssn);
  void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
@@@ -544,7 -564,6 +545,7 @@@ struct ath_ant_comb 
  #define SC_OP_BT_PRIORITY_DETECTED   BIT(12)
  #define SC_OP_BT_SCAN              BIT(13)
  #define SC_OP_ANI_RUN              BIT(14)
 +#define SC_OP_ENABLE_APM           BIT(15)
  
  /* Powersave flags */
  #define PS_WAIT_FOR_BEACON        BIT(0)
@@@ -582,14 -601,13 +583,14 @@@ struct ath_softc 
        struct ath_hw *sc_ah;
        void __iomem *mem;
        int irq;
 -      spinlock_t sc_resetlock;
        spinlock_t sc_serial_rw;
        spinlock_t sc_pm_lock;
 +      spinlock_t sc_pcu_lock;
        struct mutex mutex;
        struct work_struct paprd_work;
        struct work_struct hw_check_work;
        struct completion paprd_complete;
 +      bool paprd_pending;
  
        u32 intrstatus;
        u32 sc_flags; /* SC_OP_* */
        struct ath_descdma txsdma;
  
        struct ath_ant_comb ant_comb;
+       struct pm_qos_request_list pm_qos_req;
  };
  
  struct ath_wiphy {
        bool idle;
        int chan_idx;
        int chan_is_ht;
 +      int last_rssi;
  };
  
  void ath9k_tasklet(unsigned long data);
  int ath_reset(struct ath_softc *sc, bool retry_tx);
 -int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
  int ath_cabq_update(struct ath_softc *);
  
  static inline void ath_read_cachesize(struct ath_common *common, int *csz)
  }
  
  extern struct ieee80211_ops ath9k_ops;
- extern struct pm_qos_request_list ath9k_pm_qos_req;
  extern int modparam_nohwcrypt;
  extern int led_blink;
  
@@@ -696,12 -715,10 +698,12 @@@ static inline void ath_ahb_exit(void) {
  void ath9k_ps_wakeup(struct ath_softc *sc);
  void ath9k_ps_restore(struct ath_softc *sc);
  
 +u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
 +
  void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
  int ath9k_wiphy_add(struct ath_softc *sc);
  int ath9k_wiphy_del(struct ath_wiphy *aphy);
 -void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb);
 +void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, int ftype);
  int ath9k_wiphy_pause(struct ath_wiphy *aphy);
  int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
  int ath9k_wiphy_select(struct ath_wiphy *aphy);
index 7755fb996caaed6a327ecaa3841a2a8b23c14e6e,dd59f09441a3cdf00cbc805a36e4734d58a04253..8b9885b5243f059a6f7e4a6e6ab2ebfdcf534412
  
  #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
  
+ #define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f)
+ #define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03)
+ #define LNA_CTL_BUF_MODE      BIT(0)
+ #define LNA_CTL_ISEL_LO               BIT(1)
+ #define LNA_CTL_ISEL_HI               BIT(2)
+ #define LNA_CTL_BUF_IN                BIT(3)
+ #define LNA_CTL_FEM_BAND      BIT(4)
+ #define LNA_CTL_LOCAL_BIAS    BIT(5)
+ #define LNA_CTL_FORCE_XPA     BIT(6)
+ #define LNA_CTL_USE_ANT1      BIT(7)
  enum eeprom_param {
        EEP_NFTHRESH_5,
        EEP_NFTHRESH_2,
        EEP_PAPRD,
        EEP_MODAL_VER,
        EEP_ANT_DIV_CTL1,
 +      EEP_CHAIN_MASK_REDUCE
  };
  
  enum ar5416_rates {
@@@ -379,10 -390,7 +391,7 @@@ struct modal_eep_header 
        u8 xatten2Margin[AR5416_MAX_CHAINS];
        u8 ob_ch1;
        u8 db_ch1;
-       u8 useAnt1:1,
-           force_xpaon:1,
-           local_bias:1,
-           femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
+       u8 lna_ctl;
        u8 miscBits;
        u16 xpaBiasLvlFreq[3];
        u8 futureModal[6];
@@@ -536,18 -544,10 +545,10 @@@ struct cal_target_power_ht 
        u8 tPow2x[8];
  } __packed;
  
- #ifdef __BIG_ENDIAN_BITFIELD
- struct cal_ctl_edges {
-       u8 bChannel;
-       u8 flag:2, tPower:6;
- } __packed;
- #else
  struct cal_ctl_edges {
        u8 bChannel;
-       u8 tPower:6, flag:2;
+       u8 ctl;
  } __packed;
- #endif
  
  struct cal_data_op_loop_ar9287 {
        u8 pwrPdg[2][5];
@@@ -681,8 -681,7 +682,8 @@@ struct eeprom_ops 
        void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
        void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
                           u16 cfgCtl, u8 twiceAntennaReduction,
 -                         u8 twiceMaxRegulatoryPower, u8 powerLimit);
 +                         u8 twiceMaxRegulatoryPower, u8 powerLimit,
 +                         bool test);
        u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
  };
  
index e94216e1e107684b3cee23320b401dedff60c732,526d7c933f7fe56edf4fac310af8b5426e18e0b2..45f70b2404a19c48af7604bc02f1d61a8b27c5d3
@@@ -451,9 -451,10 +451,10 @@@ static void ath9k_hw_def_set_board_valu
                ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
                                          AR_AN_TOP2_LOCALBIAS,
                                          AR_AN_TOP2_LOCALBIAS_S,
-                                         pModal->local_bias);
+                                         !!(pModal->lna_ctl &
+                                            LNA_CTL_LOCAL_BIAS));
                REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
-                             pModal->force_xpaon);
+                             !!(pModal->lna_ctl & LNA_CTL_FORCE_XPA));
        }
  
        REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
@@@ -1021,16 -1022,13 +1022,16 @@@ static void ath9k_hw_set_def_power_per_
                0, {0, 0, 0, 0}
        };
        u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
 -      u16 ctlModesFor11a[] =
 -              { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
 -      u16 ctlModesFor11g[] =
 -              { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
 -                CTL_2GHT40
 -              };
 -      u16 numCtlModes, *pCtlMode, ctlMode, freq;
 +      static const u16 ctlModesFor11a[] = {
 +              CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
 +      };
 +      static const u16 ctlModesFor11g[] = {
 +              CTL_11B, CTL_11G, CTL_2GHT20,
 +              CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
 +      };
 +      u16 numCtlModes;
 +      const u16 *pCtlMode;
 +      u16 ctlMode, freq;
        struct chan_centers centers;
        int tx_chainmask;
        u16 twiceMinEdgePower;
@@@ -1261,7 -1259,7 +1262,7 @@@ static void ath9k_hw_def_set_txpower(st
                                    u16 cfgCtl,
                                    u8 twiceAntennaReduction,
                                    u8 twiceMaxRegulatoryPower,
 -                                  u8 powerLimit)
 +                                  u8 powerLimit, bool test)
  {
  #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
        struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  
        ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
  
 +      regulatory->max_power_level = 0;
        for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
                ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
                if (ratesArray[i] > AR5416_MAX_RATE_POWER)
                        ratesArray[i] = AR5416_MAX_RATE_POWER;
 +              if (ratesArray[i] > regulatory->max_power_level)
 +                      regulatory->max_power_level = ratesArray[i];
 +      }
 +
 +      if (!test) {
 +              i = rate6mb;
 +
 +              if (IS_CHAN_HT40(chan))
 +                      i = rateHt40_0;
 +              else if (IS_CHAN_HT20(chan))
 +                      i = rateHt20_0;
 +
 +              regulatory->max_power_level = ratesArray[i];
 +      }
 +
 +      switch(ar5416_get_ntxchains(ah->txchainmask)) {
 +      case 1:
 +              break;
 +      case 2:
 +              regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
 +              break;
 +      case 3:
 +              regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
 +              break;
 +      default:
 +              ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM,
 +                        "Invalid chainmask configuration\n");
 +              break;
        }
  
 +      if (test)
 +              return;
 +
        if (AR_SREV_9280_20_OR_LATER(ah)) {
                for (i = 0; i < Ar5416RateSize; i++) {
                        int8_t pwr_table_offset;
        REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
                  ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
                  | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
 -
 -      i = rate6mb;
 -
 -      if (IS_CHAN_HT40(chan))
 -              i = rateHt40_0;
 -      else if (IS_CHAN_HT20(chan))
 -              i = rateHt20_0;
 -
 -      if (AR_SREV_9280_20_OR_LATER(ah))
 -              regulatory->max_power_level =
 -                      ratesArray[i] + AR5416_PWR_TABLE_OFFSET_DB * 2;
 -      else
 -              regulatory->max_power_level = ratesArray[i];
 -
 -      switch(ar5416_get_ntxchains(ah->txchainmask)) {
 -      case 1:
 -              break;
 -      case 2:
 -              regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
 -              break;
 -      case 3:
 -              regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
 -              break;
 -      default:
 -              ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM,
 -                        "Invalid chainmask configuration\n");
 -              break;
 -      }
  }
  
  static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
  
        num_ant_config = 1;
  
-       if (pBase->version >= 0x0E0D)
-               if (pModal->useAnt1)
-                       num_ant_config += 1;
+       if (pBase->version >= 0x0E0D &&
+           (pModal->lna_ctl & LNA_CTL_USE_ANT1))
+               num_ant_config += 1;
  
        return num_ant_config;
  }
index b4396a9578e56c3e24b52cc6b4b09e3adbadeda2,c7fbe25cc12827cf29f68729fe636b07ef75ebfa..9b1ee7fc05c1ae88037366d1ede69e0bec5793b4
@@@ -310,9 -310,10 +310,9 @@@ static bool ath9k_hw_chip_test(struct a
        struct ath_common *common = ath9k_hw_common(ah);
        u32 regAddr[2] = { AR_STA_ID0 };
        u32 regHold[2];
 -      u32 patternData[4] = { 0x55555555,
 -                             0xaaaaaaaa,
 -                             0x66666666,
 -                             0x99999999 };
 +      static const u32 patternData[4] = {
 +              0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
 +      };
        int i, j, loop_max;
  
        if (!AR_SREV_9300_20_OR_LATER(ah)) {
@@@ -418,6 -419,10 +418,6 @@@ static void ath9k_hw_init_defaults(stru
        ah->hw_version.magic = AR5416_MAGIC;
        ah->hw_version.subvendorid = 0;
  
 -      ah->ah_flags = 0;
 -      if (!AR_SREV_9100(ah))
 -              ah->ah_flags = AH_USE_EEPROM;
 -
        ah->atim_window = 0;
        ah->sta_id1_defaults =
                AR_STA_ID1_CRPT_MIC_ENABLE |
@@@ -435,7 -440,7 +435,7 @@@ static int ath9k_hw_init_macaddr(struc
        u32 sum;
        int i;
        u16 eeval;
 -      u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
 +      static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
  
        sum = 0;
        for (i = 0; i < 3; i++) {
@@@ -1165,7 -1170,7 +1165,7 @@@ static bool ath9k_hw_channel_change(str
                             channel->max_antenna_gain * 2,
                             channel->max_power * 2,
                             min((u32) MAX_RATE_POWER,
 -                           (u32) regulatory->power_limit));
 +                           (u32) regulatory->power_limit), false);
  
        ath9k_hw_rfbus_done(ah);
  
@@@ -1828,10 -1833,6 +1828,10 @@@ int ath9k_hw_fill_cap_info(struct ath_h
  
        ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
  
 +      /* enable key search for every frame in an aggregate */
 +      if (AR_SREV_9300_20_OR_LATER(ah))
 +              ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
 +
        pCap->low_2ghz_chan = 2312;
        pCap->high_2ghz_chan = 2732;
  
        pCap->num_antcfg_2ghz =
                ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
  
 -      if (AR_SREV_9280_20_OR_LATER(ah) &&
 -          ath9k_hw_btcoex_supported(ah)) {
 +      if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) {
                btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
                btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
  
        if (AR_SREV_9300_20_OR_LATER(ah))
                pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
  
 +      if (AR_SREV_9300_20_OR_LATER(ah))
 +              ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
 +
        if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
                pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
  
                        if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
                                pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
                }
 +      if (AR_SREV_9300_20_OR_LATER(ah)) {
 +              if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
 +                      pCap->hw_caps |= ATH9K_HW_CAP_APM;
 +      }
 +
 +
  
        return 0;
  }
@@@ -2051,7 -2044,8 +2051,8 @@@ u32 ath9k_hw_gpio_get(struct ath_hw *ah
                val = REG_READ(ah, AR7010_GPIO_IN);
                return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
        } else if (AR_SREV_9300_20_OR_LATER(ah))
-               return MS_REG_READ(AR9300, gpio) != 0;
+               return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
+                       AR_GPIO_BIT(gpio)) != 0;
        else if (AR_SREV_9271(ah))
                return MS_REG_READ(AR9271, gpio) != 0;
        else if (AR_SREV_9287_11_OR_LATER(ah))
@@@ -2183,7 -2177,7 +2184,7 @@@ bool ath9k_hw_disable(struct ath_hw *ah
  }
  EXPORT_SYMBOL(ath9k_hw_disable);
  
 -void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
 +void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
  {
        struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
        struct ath9k_channel *chan = ah->curchan;
                                 channel->max_antenna_gain * 2,
                                 channel->max_power * 2,
                                 min((u32) MAX_RATE_POWER,
 -                               (u32) regulatory->power_limit));
 +                               (u32) regulatory->power_limit), test);
  }
  EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
  
@@@ -2330,10 -2324,11 +2331,10 @@@ static u32 rightmost_index(struct ath_g
        return timer_table->gen_timer_index[b];
  }
  
 -u32 ath9k_hw_gettsf32(struct ath_hw *ah)
 +static u32 ath9k_hw_gettsf32(struct ath_hw *ah)
  {
        return REG_READ(ah, AR_TSF_L32);
  }
 -EXPORT_SYMBOL(ath9k_hw_gettsf32);
  
  struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
                                          void (*trigger)(void *),
index ef39a4551bd5f8e5dad8f5224e70b7e4625149ac,14b8ab386daff8823bcc3301fa52d467ce6cb01b..918308a2841055010f0263a53513cfb8a95db2b4
@@@ -15,7 -15,6 +15,6 @@@
   */
  
  #include <linux/slab.h>
- #include <linux/pm_qos_params.h>
  
  #include "ath9k.h"
  
@@@ -38,10 -37,6 +37,10 @@@ int led_blink
  module_param_named(blink, led_blink, int, 0444);
  MODULE_PARM_DESC(blink, "Enable LED blink on activity");
  
 +static int ath9k_btcoex_enable;
 +module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
 +MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
 +
  /* We use the hw_value as an index into our private channel structure */
  
  #define CHAN2G(_freq, _idx)  { \
@@@ -184,8 -179,6 +183,6 @@@ static const struct ath_ops ath9k_commo
        .write = ath9k_iowrite32,
  };
  
- struct pm_qos_request_list ath9k_pm_qos_req;
  /**************************/
  /*     Initialization     */
  /**************************/
@@@ -402,8 -395,7 +399,8 @@@ static void ath9k_init_crypto(struct at
  
  static int ath9k_init_btcoex(struct ath_softc *sc)
  {
 -      int r, qnum;
 +      struct ath_txq *txq;
 +      int r;
  
        switch (sc->sc_ah->btcoex_hw.scheme) {
        case ATH_BTCOEX_CFG_NONE:
                r = ath_init_btcoex_timer(sc);
                if (r)
                        return -1;
 -              qnum = sc->tx.hwq_map[WME_AC_BE];
 -              ath9k_hw_init_btcoex_hw(sc->sc_ah, qnum);
 +              txq = sc->tx.txq_map[WME_AC_BE];
 +              ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum);
                sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
                break;
        default:
  
  static int ath9k_init_queues(struct ath_softc *sc)
  {
 -      struct ath_common *common = ath9k_hw_common(sc->sc_ah);
        int i = 0;
  
 -      for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
 -              sc->tx.hwq_map[i] = -1;
 -
        sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
 -      if (sc->beacon.beaconq == -1) {
 -              ath_print(common, ATH_DBG_FATAL,
 -                        "Unable to setup a beacon xmit queue\n");
 -              goto err;
 -      }
 -
        sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
 -      if (sc->beacon.cabq == NULL) {
 -              ath_print(common, ATH_DBG_FATAL,
 -                        "Unable to setup CAB xmit queue\n");
 -              goto err;
 -      }
  
        sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
        ath_cabq_update(sc);
  
 -      if (!ath_tx_setup(sc, WME_AC_BK)) {
 -              ath_print(common, ATH_DBG_FATAL,
 -                        "Unable to setup xmit queue for BK traffic\n");
 -              goto err;
 -      }
 -
 -      if (!ath_tx_setup(sc, WME_AC_BE)) {
 -              ath_print(common, ATH_DBG_FATAL,
 -                        "Unable to setup xmit queue for BE traffic\n");
 -              goto err;
 -      }
 -      if (!ath_tx_setup(sc, WME_AC_VI)) {
 -              ath_print(common, ATH_DBG_FATAL,
 -                        "Unable to setup xmit queue for VI traffic\n");
 -              goto err;
 -      }
 -      if (!ath_tx_setup(sc, WME_AC_VO)) {
 -              ath_print(common, ATH_DBG_FATAL,
 -                        "Unable to setup xmit queue for VO traffic\n");
 -              goto err;
 -      }
 +      for (i = 0; i < WME_NUM_AC; i++)
 +              sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
  
        return 0;
 -
 -err:
 -      for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
 -              if (ATH_TXQ_SETUP(sc, i))
 -                      ath_tx_cleanupq(sc, &sc->tx.txq[i]);
 -
 -      return -EIO;
  }
  
  static int ath9k_init_channels_rates(struct ath_softc *sc)
@@@ -537,9 -570,6 +534,9 @@@ static int ath9k_init_softc(u16 devid, 
        ah->hw_version.subsysid = subsysid;
        sc->sc_ah = ah;
  
 +      if (!sc->dev->platform_data)
 +              ah->ah_flags |= AH_USE_EEPROM;
 +
        common = ath9k_hw_common(ah);
        common->ops = &ath9k_common_ops;
        common->bus_ops = bus_ops;
        common->hw = sc->hw;
        common->priv = sc;
        common->debug_mask = ath9k_debug;
 +      common->btcoex_enabled = ath9k_btcoex_enable == 1;
        spin_lock_init(&common->cc_lock);
  
        spin_lock_init(&sc->wiphy_lock);
 -      spin_lock_init(&sc->sc_resetlock);
        spin_lock_init(&sc->sc_serial_rw);
        spin_lock_init(&sc->sc_pm_lock);
        mutex_init(&sc->mutex);
        if (ret)
                goto err_hw;
  
 -      ret = ath9k_init_debug(ah);
 -      if (ret) {
 -              ath_print(common, ATH_DBG_FATAL,
 -                        "Unable to create debugfs files\n");
 -              goto err_debug;
 -      }
 -
        ret = ath9k_init_queues(sc);
        if (ret)
                goto err_queues;
@@@ -592,6 -629,8 +589,6 @@@ err_btcoex
                if (ATH_TXQ_SETUP(sc, i))
                        ath_tx_cleanupq(sc, &sc->tx.txq[i]);
  err_queues:
 -      ath9k_exit_debug(ah);
 -err_debug:
        ath9k_hw_deinit(ah);
  err_hw:
        tasklet_kill(&sc->intr_tq);
        return ret;
  }
  
 +static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
 +{
 +      struct ieee80211_supported_band *sband;
 +      struct ieee80211_channel *chan;
 +      struct ath_hw *ah = sc->sc_ah;
 +      struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
 +      int i;
 +
 +      sband = &sc->sbands[band];
 +      for (i = 0; i < sband->n_channels; i++) {
 +              chan = &sband->channels[i];
 +              ah->curchan = &ah->channels[chan->hw_value];
 +              ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20);
 +              ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
 +              chan->max_power = reg->max_power_level / 2;
 +      }
 +}
 +
 +static void ath9k_init_txpower_limits(struct ath_softc *sc)
 +{
 +      struct ath_hw *ah = sc->sc_ah;
 +      struct ath9k_channel *curchan = ah->curchan;
 +
 +      if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
 +              ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
 +      if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
 +              ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
 +
 +      ah->curchan = curchan;
 +}
 +
  void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
  {
        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
                hw->flags |= IEEE80211_HW_MFP_CAPABLE;
  
        hw->wiphy->interface_modes =
+               BIT(NL80211_IFTYPE_P2P_GO) |
+               BIT(NL80211_IFTYPE_P2P_CLIENT) |
                BIT(NL80211_IFTYPE_AP) |
                BIT(NL80211_IFTYPE_WDS) |
                BIT(NL80211_IFTYPE_STATION) |
@@@ -695,7 -705,6 +694,7 @@@ int ath9k_init_device(u16 devid, struc
                    const struct ath_bus_ops *bus_ops)
  {
        struct ieee80211_hw *hw = sc->hw;
 +      struct ath_wiphy *aphy = hw->priv;
        struct ath_common *common;
        struct ath_hw *ah;
        int error = 0;
        if (error != 0)
                goto error_rx;
  
 +      ath9k_init_txpower_limits(sc);
 +
        /* Register with mac80211 */
        error = ieee80211_register_hw(hw);
        if (error)
                goto error_register;
  
 +      error = ath9k_init_debug(ah);
 +      if (error) {
 +              ath_print(common, ATH_DBG_FATAL,
 +                        "Unable to create debugfs files\n");
 +              goto error_world;
 +      }
 +
        /* Handle world regulatory */
        if (!ath_is_world_regd(reg)) {
                error = regulatory_hint(hw->wiphy, reg->alpha2);
        INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
        INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
        sc->wiphy_scheduler_int = msecs_to_jiffies(500);
 +      aphy->last_rssi = ATH_RSSI_DUMMY_MARKER;
  
        ath_init_leds(sc);
        ath_start_rfkill_poll(sc);
  
-       pm_qos_add_request(&ath9k_pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
+       pm_qos_add_request(&sc->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
                           PM_QOS_DEFAULT_VALUE);
  
        return 0;
@@@ -800,6 -799,7 +799,6 @@@ static void ath9k_deinit_softc(struct a
                if (ATH_TXQ_SETUP(sc, i))
                        ath_tx_cleanupq(sc, &sc->tx.txq[i]);
  
 -      ath9k_exit_debug(sc->sc_ah);
        ath9k_hw_deinit(sc->sc_ah);
  
        tasklet_kill(&sc->intr_tq);
@@@ -829,7 -829,7 +828,7 @@@ void ath9k_deinit_device(struct ath_sof
        }
  
        ieee80211_unregister_hw(hw);
-       pm_qos_remove_request(&ath9k_pm_qos_req);
+       pm_qos_remove_request(&sc->pm_qos_req);
        ath_rx_cleanup(sc);
        ath_tx_cleanup(sc);
        ath9k_deinit_softc(sc);
@@@ -866,12 -866,20 +865,12 @@@ static int __init ath9k_init(void
                goto err_out;
        }
  
 -      error = ath9k_debug_create_root();
 -      if (error) {
 -              printk(KERN_ERR
 -                      "ath9k: Unable to create debugfs root: %d\n",
 -                      error);
 -              goto err_rate_unregister;
 -      }
 -
        error = ath_pci_init();
        if (error < 0) {
                printk(KERN_ERR
                        "ath9k: No PCI devices found, driver not installed.\n");
                error = -ENODEV;
 -              goto err_remove_root;
 +              goto err_rate_unregister;
        }
  
        error = ath_ahb_init();
   err_pci_exit:
        ath_pci_exit();
  
 - err_remove_root:
 -      ath9k_debug_remove_root();
   err_rate_unregister:
        ath_rate_control_unregister();
   err_out:
@@@ -896,6 -906,7 +895,6 @@@ static void __exit ath9k_exit(void
  {
        ath_ahb_exit();
        ath_pci_exit();
 -      ath9k_debug_remove_root();
        ath_rate_control_unregister();
        printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
  }
index df1bfcfeb7343b327bbf4a543281ee745440972e,dace215b693eb553bbb713a3ce1cdada28148683..f026a031713b8e03b979bf95b724b965f3b97e8f
@@@ -15,7 -15,6 +15,6 @@@
   */
  
  #include <linux/nl80211.h>
- #include <linux/pm_qos_params.h>
  #include "ath9k.h"
  #include "btcoex.h"
  
@@@ -24,7 -23,7 +23,7 @@@ static void ath_update_txpow(struct ath
        struct ath_hw *ah = sc->sc_ah;
  
        if (sc->curtxpow != sc->config.txpowlimit) {
 -              ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
 +              ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
                /* read back in case value is clamped */
                sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
        }
@@@ -235,8 -234,6 +234,8 @@@ int ath_set_channel(struct ath_softc *s
  
        ath9k_ps_wakeup(sc);
  
 +      spin_lock_bh(&sc->sc_pcu_lock);
 +
        /*
         * This is only performed if the channel settings have
         * actually changed.
         * hardware at the new frequency, and then re-enable
         * the relevant bits of the h/w.
         */
 -      ath9k_hw_set_interrupts(ah, 0);
 +      ath9k_hw_disable_interrupts(ah);
        ath_drain_all_txq(sc, false);
  
 -      spin_lock_bh(&sc->rx.pcu_lock);
 -
        stopped = ath_stoprecv(sc);
  
        /* XXX: do not flush receive queue here. We don't want
                  channel->center_freq, conf_is_ht40(conf),
                  fastcc);
  
 -      spin_lock_bh(&sc->sc_resetlock);
 -
        r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
        if (r) {
                ath_print(common, ATH_DBG_FATAL,
                          "Unable to reset channel (%u MHz), "
                          "reset status %d\n",
                          channel->center_freq, r);
 -              spin_unlock_bh(&sc->sc_resetlock);
 -              spin_unlock_bh(&sc->rx.pcu_lock);
                goto ps_restore;
        }
 -      spin_unlock_bh(&sc->sc_resetlock);
  
        if (ath_startrecv(sc) != 0) {
                ath_print(common, ATH_DBG_FATAL,
                          "Unable to restart recv logic\n");
                r = -EIO;
 -              spin_unlock_bh(&sc->rx.pcu_lock);
                goto ps_restore;
        }
  
 -      spin_unlock_bh(&sc->rx.pcu_lock);
 -
        ath_update_txpow(sc);
        ath9k_hw_set_interrupts(ah, ah->imask);
  
        }
  
   ps_restore:
 +      spin_unlock_bh(&sc->sc_pcu_lock);
 +
        ath9k_ps_restore(sc);
        return r;
  }
@@@ -335,7 -340,7 +334,7 @@@ void ath_paprd_calibrate(struct work_st
        struct ath_tx_control txctl;
        struct ath9k_hw_cal_data *caldata = ah->caldata;
        struct ath_common *common = ath9k_hw_common(ah);
 -      int qnum, ftype;
 +      int ftype;
        int chain_ok = 0;
        int chain;
        int len = 1800;
        memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
  
        memset(&txctl, 0, sizeof(txctl));
 -      qnum = sc->tx.hwq_map[WME_AC_BE];
 -      txctl.txq = &sc->tx.txq[qnum];
 +      txctl.txq = sc->tx.txq_map[WME_AC_BE];
  
        ath9k_ps_wakeup(sc);
        ar9003_paprd_init_table(ah);
                }
  
                init_completion(&sc->paprd_complete);
 +              sc->paprd_pending = true;
                ar9003_paprd_setup_gain_table(ah, chain);
                txctl.paprd = BIT(chain);
                if (ath_tx_start(hw, skb, &txctl) != 0)
  
                time_left = wait_for_completion_timeout(&sc->paprd_complete,
                                msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
 +              sc->paprd_pending = false;
                if (!time_left) {
                        ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
                                  "Timeout waiting for paprd training on "
@@@ -554,17 -558,15 +553,17 @@@ void ath_update_chainmask(struct ath_so
  static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
  {
        struct ath_node *an;
 -
 +      struct ath_hw *ah = sc->sc_ah;
        an = (struct ath_node *)sta->drv_priv;
  
 +      if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM)
 +              sc->sc_flags |= SC_OP_ENABLE_APM;
 +
        if (sc->sc_flags & SC_OP_TXAGGR) {
                ath_tx_node_init(sc, an);
                an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
                                     sta->ht_cap.ampdu_factor);
                an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 -              an->last_rssi = ATH_RSSI_DUMMY_MARKER;
        }
  }
  
@@@ -612,8 -614,6 +611,8 @@@ void ath9k_tasklet(unsigned long data
                return;
        }
  
 +      spin_lock_bh(&sc->sc_pcu_lock);
 +
        if (!ath9k_hw_check_alive(ah))
                ieee80211_queue_work(sc->hw, &sc->hw_check_work);
  
                rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  
        if (status & rxmask) {
 -              spin_lock_bh(&sc->rx.pcu_lock);
 -
                /* Check for high priority Rx first */
                if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
                    (status & ATH9K_INT_RXHP))
                        ath_rx_tasklet(sc, 0, true);
  
                ath_rx_tasklet(sc, 0, false);
 -              spin_unlock_bh(&sc->rx.pcu_lock);
        }
  
        if (status & ATH9K_INT_TX) {
                        ath_gen_timer_isr(sc->sc_ah);
  
        /* re-enable hardware interrupt */
 -      ath9k_hw_set_interrupts(ah, ah->imask);
 +      ath9k_hw_enable_interrupts(ah);
 +
 +      spin_unlock_bh(&sc->sc_pcu_lock);
        ath9k_ps_restore(sc);
  }
  
@@@ -755,7 -756,7 +754,7 @@@ irqreturn_t ath_isr(int irq, void *dev
                 * interrupt; otherwise it will continue to
                 * fire.
                 */
 -              ath9k_hw_set_interrupts(ah, 0);
 +              ath9k_hw_disable_interrupts(ah);
                /*
                 * Let the hal handle the event. We assume
                 * it will clear whatever condition caused
                spin_lock(&common->cc_lock);
                ath9k_hw_proc_mib_event(ah);
                spin_unlock(&common->cc_lock);
 -              ath9k_hw_set_interrupts(ah, ah->imask);
 +              ath9k_hw_enable_interrupts(ah);
        }
  
        if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
@@@ -781,8 -782,8 +780,8 @@@ chip_reset
        ath_debug_stat_interrupt(sc, status);
  
        if (sched) {
 -              /* turn off every interrupt except SWBA */
 -              ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA));
 +              /* turn off every interrupt */
 +              ath9k_hw_disable_interrupts(ah);
                tasklet_schedule(&sc->intr_tq);
        }
  
@@@ -834,11 -835,9 +833,11 @@@ static u32 ath_get_extchanmode(struct a
  }
  
  static void ath9k_bss_assoc_info(struct ath_softc *sc,
 +                               struct ieee80211_hw *hw,
                                 struct ieee80211_vif *vif,
                                 struct ieee80211_bss_conf *bss_conf)
  {
 +      struct ath_wiphy *aphy = hw->priv;
        struct ath_hw *ah = sc->sc_ah;
        struct ath_common *common = ath9k_hw_common(ah);
  
                ath_beacon_config(sc, vif);
  
                /* Reset rssi stats */
 +              aphy->last_rssi = ATH_RSSI_DUMMY_MARKER;
                sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  
                sc->sc_flags |= SC_OP_ANI_RUN;
@@@ -884,13 -882,13 +883,13 @@@ void ath_radio_enable(struct ath_softc 
        int r;
  
        ath9k_ps_wakeup(sc);
 +      spin_lock_bh(&sc->sc_pcu_lock);
 +
        ath9k_hw_configpcipowersave(ah, 0, 0);
  
        if (!ah->curchan)
                ah->curchan = ath_get_curchannel(sc, sc->hw);
  
 -      spin_lock_bh(&sc->rx.pcu_lock);
 -      spin_lock_bh(&sc->sc_resetlock);
        r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
        if (r) {
                ath_print(common, ATH_DBG_FATAL,
                          "reset status %d\n",
                          channel->center_freq, r);
        }
 -      spin_unlock_bh(&sc->sc_resetlock);
  
        ath_update_txpow(sc);
        if (ath_startrecv(sc) != 0) {
                ath_print(common, ATH_DBG_FATAL,
                          "Unable to restart recv logic\n");
 -              spin_unlock_bh(&sc->rx.pcu_lock);
 +              spin_unlock_bh(&sc->sc_pcu_lock);
                return;
        }
 -      spin_unlock_bh(&sc->rx.pcu_lock);
 -
        if (sc->sc_flags & SC_OP_BEACONS)
                ath_beacon_config(sc, NULL);    /* restart beacons */
  
        ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  
        ieee80211_wake_queues(hw);
 +      spin_unlock_bh(&sc->sc_pcu_lock);
 +
        ath9k_ps_restore(sc);
  }
  
@@@ -930,8 -929,6 +929,8 @@@ void ath_radio_disable(struct ath_soft
        int r;
  
        ath9k_ps_wakeup(sc);
 +      spin_lock_bh(&sc->sc_pcu_lock);
 +
        ieee80211_stop_queues(hw);
  
        /*
        }
  
        /* Disable interrupts */
 -      ath9k_hw_set_interrupts(ah, 0);
 +      ath9k_hw_disable_interrupts(ah);
  
        ath_drain_all_txq(sc, false);   /* clear pending tx frames */
  
 -      spin_lock_bh(&sc->rx.pcu_lock);
 -
        ath_stoprecv(sc);               /* turn off frame recv */
        ath_flushrecv(sc);              /* flush recv queue */
  
        if (!ah->curchan)
                ah->curchan = ath_get_curchannel(sc, hw);
  
 -      spin_lock_bh(&sc->sc_resetlock);
        r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
        if (r) {
                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
                          "reset status %d\n",
                          channel->center_freq, r);
        }
 -      spin_unlock_bh(&sc->sc_resetlock);
  
        ath9k_hw_phy_disable(ah);
  
 -      spin_unlock_bh(&sc->rx.pcu_lock);
 -
        ath9k_hw_configpcipowersave(ah, 1, 1);
 +
 +      spin_unlock_bh(&sc->sc_pcu_lock);
        ath9k_ps_restore(sc);
 +
        ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  }
  
@@@ -982,25 -982,29 +981,25 @@@ int ath_reset(struct ath_softc *sc, boo
        /* Stop ANI */
        del_timer_sync(&common->ani.timer);
  
 +      spin_lock_bh(&sc->sc_pcu_lock);
 +
        ieee80211_stop_queues(hw);
  
 -      ath9k_hw_set_interrupts(ah, 0);
 +      ath9k_hw_disable_interrupts(ah);
        ath_drain_all_txq(sc, retry_tx);
  
 -      spin_lock_bh(&sc->rx.pcu_lock);
 -
        ath_stoprecv(sc);
        ath_flushrecv(sc);
  
 -      spin_lock_bh(&sc->sc_resetlock);
        r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
        if (r)
                ath_print(common, ATH_DBG_FATAL,
                          "Unable to reset hardware; reset status %d\n", r);
 -      spin_unlock_bh(&sc->sc_resetlock);
  
        if (ath_startrecv(sc) != 0)
                ath_print(common, ATH_DBG_FATAL,
                          "Unable to start recv logic\n");
  
 -      spin_unlock_bh(&sc->rx.pcu_lock);
 -
        /*
         * We may be doing a reset in response to a request
         * that changes the channel so update any state that
        }
  
        ieee80211_wake_queues(hw);
 +      spin_unlock_bh(&sc->sc_pcu_lock);
  
        /* Start ANI */
        ath_start_ani(common);
        return r;
  }
  
 -static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
 -{
 -      int qnum;
 -
 -      switch (queue) {
 -      case 0:
 -              qnum = sc->tx.hwq_map[WME_AC_VO];
 -              break;
 -      case 1:
 -              qnum = sc->tx.hwq_map[WME_AC_VI];
 -              break;
 -      case 2:
 -              qnum = sc->tx.hwq_map[WME_AC_BE];
 -              break;
 -      case 3:
 -              qnum = sc->tx.hwq_map[WME_AC_BK];
 -              break;
 -      default:
 -              qnum = sc->tx.hwq_map[WME_AC_BE];
 -              break;
 -      }
 -
 -      return qnum;
 -}
 -
 -int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
 -{
 -      int qnum;
 -
 -      switch (queue) {
 -      case WME_AC_VO:
 -              qnum = 0;
 -              break;
 -      case WME_AC_VI:
 -              qnum = 1;
 -              break;
 -      case WME_AC_BE:
 -              qnum = 2;
 -              break;
 -      case WME_AC_BK:
 -              qnum = 3;
 -              break;
 -      default:
 -              qnum = -1;
 -              break;
 -      }
 -
 -      return qnum;
 -}
 -
  /* XXX: Remove me once we don't depend on ath9k_channel for all
   * this redundant data */
  void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
@@@ -1114,16 -1167,19 +1113,16 @@@ static int ath9k_start(struct ieee80211
         * be followed by initialization of the appropriate bits
         * and then setup of the interrupt mask.
         */
 -      spin_lock_bh(&sc->rx.pcu_lock);
 -      spin_lock_bh(&sc->sc_resetlock);
 +      spin_lock_bh(&sc->sc_pcu_lock);
        r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
        if (r) {
                ath_print(common, ATH_DBG_FATAL,
                          "Unable to reset hardware; reset status %d "
                          "(freq %u MHz)\n", r,
                          curchan->center_freq);
 -              spin_unlock_bh(&sc->sc_resetlock);
 -              spin_unlock_bh(&sc->rx.pcu_lock);
 +              spin_unlock_bh(&sc->sc_pcu_lock);
                goto mutex_unlock;
        }
 -      spin_unlock_bh(&sc->sc_resetlock);
  
        /*
         * This is needed only to setup initial state
                ath_print(common, ATH_DBG_FATAL,
                          "Unable to start recv logic\n");
                r = -EIO;
 -              spin_unlock_bh(&sc->rx.pcu_lock);
 +              spin_unlock_bh(&sc->sc_pcu_lock);
                goto mutex_unlock;
        }
 -      spin_unlock_bh(&sc->rx.pcu_lock);
 +      spin_unlock_bh(&sc->sc_pcu_lock);
  
        /* Setup our intr mask. */
        ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
                        ath9k_btcoex_timer_resume(sc);
        }
  
-       pm_qos_update_request(&ath9k_pm_qos_req, 55);
+       pm_qos_update_request(&sc->pm_qos_req, 55);
  
  mutex_unlock:
        mutex_unlock(&sc->mutex);
  static int ath9k_tx(struct ieee80211_hw *hw,
                    struct sk_buff *skb)
  {
 -      struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
        struct ath_wiphy *aphy = hw->priv;
        struct ath_softc *sc = aphy->sc;
        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
        struct ath_tx_control txctl;
 -      int padpos, padsize;
        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
 -      int qnum;
  
        if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
                ath_print(common, ATH_DBG_XMIT,
        }
  
        memset(&txctl, 0, sizeof(struct ath_tx_control));
 -
 -      /*
 -       * As a temporary workaround, assign seq# here; this will likely need
 -       * to be cleaned up to work better with Beacon transmission and virtual
 -       * BSSes.
 -       */
 -      if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
 -              if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
 -                      sc->tx.seq_no += 0x10;
 -              hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
 -              hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
 -      }
 -
 -      /* Add the padding after the header if this is not already done */
 -      padpos = ath9k_cmn_padpos(hdr->frame_control);
 -      padsize = padpos & 3;
 -      if (padsize && skb->len>padpos) {
 -              if (skb_headroom(skb) < padsize)
 -                      return -1;
 -              skb_push(skb, padsize);
 -              memmove(skb->data, skb->data + padsize, padpos);
 -      }
 -
 -      qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
 -      txctl.txq = &sc->tx.txq[qnum];
 +      txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  
        ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
  
@@@ -1316,25 -1399,22 +1315,25 @@@ static void ath9k_stop(struct ieee80211
                        ath9k_btcoex_timer_pause(sc);
        }
  
 +      spin_lock_bh(&sc->sc_pcu_lock);
 +
        /* make sure h/w will not generate any interrupt
         * before setting the invalid flag. */
 -      ath9k_hw_set_interrupts(ah, 0);
 +      ath9k_hw_disable_interrupts(ah);
  
 -      spin_lock_bh(&sc->rx.pcu_lock);
        if (!(sc->sc_flags & SC_OP_INVALID)) {
                ath_drain_all_txq(sc, false);
                ath_stoprecv(sc);
                ath9k_hw_phy_disable(ah);
        } else
                sc->rx.rxlink = NULL;
 -      spin_unlock_bh(&sc->rx.pcu_lock);
  
        /* disable HAL and put h/w to sleep */
        ath9k_hw_disable(ah);
        ath9k_hw_configpcipowersave(ah, 1, 1);
 +
 +      spin_unlock_bh(&sc->sc_pcu_lock);
 +
        ath9k_ps_restore(sc);
  
        /* Finally, put the chip in FULL SLEEP mode */
  
        sc->sc_flags |= SC_OP_INVALID;
  
-       pm_qos_update_request(&ath9k_pm_qos_req, PM_QOS_DEFAULT_VALUE);
+       pm_qos_update_request(&sc->pm_qos_req, PM_QOS_DEFAULT_VALUE);
  
        mutex_unlock(&sc->mutex);
  
@@@ -1439,6 -1519,7 +1438,7 @@@ static void ath9k_remove_interface(stru
        struct ath_softc *sc = aphy->sc;
        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
        struct ath_vif *avp = (void *)vif->drv_priv;
+       bool bs_valid = false;
        int i;
  
        ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
                               "slot\n", __func__);
                        sc->beacon.bslot[i] = NULL;
                        sc->beacon.bslot_aphy[i] = NULL;
-               }
+               } else if (sc->beacon.bslot[i])
+                       bs_valid = true;
+       }
+       if (!bs_valid && (sc->sc_ah->imask & ATH9K_INT_SWBA)) {
+               /* Disable SWBA interrupt */
+               sc->sc_ah->imask &= ~ATH9K_INT_SWBA;
+               ath9k_ps_wakeup(sc);
+               ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
+               ath9k_ps_restore(sc);
        }
  
        sc->nvifs--;
@@@ -1741,15 -1830,12 +1749,15 @@@ static int ath9k_conf_tx(struct ieee802
        struct ath_wiphy *aphy = hw->priv;
        struct ath_softc *sc = aphy->sc;
        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 +      struct ath_txq *txq;
        struct ath9k_tx_queue_info qi;
 -      int ret = 0, qnum;
 +      int ret = 0;
  
        if (queue >= WME_NUM_AC)
                return 0;
  
 +      txq = sc->tx.txq_map[queue];
 +
        mutex_lock(&sc->mutex);
  
        memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
        qi.tqi_cwmin = params->cw_min;
        qi.tqi_cwmax = params->cw_max;
        qi.tqi_burstTime = params->txop;
 -      qnum = ath_get_hal_qnum(queue, sc);
  
        ath_print(common, ATH_DBG_CONFIG,
                  "Configure tx [queue/halq] [%d/%d],  "
                  "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
 -                queue, qnum, params->aifs, params->cw_min,
 +                queue, txq->axq_qnum, params->aifs, params->cw_min,
                  params->cw_max, params->txop);
  
 -      ret = ath_txq_update(sc, qnum, &qi);
 +      ret = ath_txq_update(sc, txq->axq_qnum, &qi);
        if (ret)
                ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
  
        if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
 -              if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret)
 +              if (queue == WME_AC_BE && !ret)
                        ath_beaconq_config(sc);
  
        mutex_unlock(&sc->mutex);
@@@ -1932,7 -2019,7 +1940,7 @@@ static void ath9k_bss_info_changed(stru
        if (changed & BSS_CHANGED_ASSOC) {
                ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
                        bss_conf->assoc);
 -              ath9k_bss_assoc_info(sc, vif, bss_conf);
 +              ath9k_bss_assoc_info(sc, hw, vif, bss_conf);
        }
  
        mutex_unlock(&sc->mutex);
@@@ -1995,9 -2082,6 +2003,9 @@@ static int ath9k_ampdu_action(struct ie
        case IEEE80211_AMPDU_RX_STOP:
                break;
        case IEEE80211_AMPDU_TX_START:
 +              if (!(sc->sc_flags & SC_OP_TXAGGR))
 +                      return -EOPNOTSUPP;
 +
                ath9k_ps_wakeup(sc);
                ret = ath_tx_aggr_start(sc, sta, tid, ssn);
                if (!ret)
index a597cc8d864472139403516e93f21ed18c7ee442,2c6a22fbb0f0cf76fb5ac5cfd22b530402e9f693..c2472edab5e0b448930c1c5a56d213598d8a9dd0
       ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))
  
  #define AR_DEVID_7010(_ah) \
 -      (((_ah)->hw_version.devid == 0x7010) || \
 -       ((_ah)->hw_version.devid == 0x7015) || \
 -       ((_ah)->hw_version.devid == 0x9018) || \
 -       ((_ah)->hw_version.devid == 0xA704) || \
 -       ((_ah)->hw_version.devid == 0x1200))
 -
 -#define AR9287_HTC_DEVID(_ah) \
 -      (((_ah)->hw_version.devid == 0x7015) || \
 -       ((_ah)->hw_version.devid == 0x1200))
 +      ((_ah)->common.driver_info & AR7010_DEVICE)
  
  #define AR_RADIO_SREV_MAJOR                   0xf0
  #define AR_RAD5133_SREV_MAJOR                 0xc0
@@@ -976,11 -984,13 +976,13 @@@ enum 
  #define AR9287_GPIO_IN_VAL_S                     11
  #define AR9271_GPIO_IN_VAL                       0xFFFF0000
  #define AR9271_GPIO_IN_VAL_S                     16
- #define AR9300_GPIO_IN_VAL                       0x0001FFFF
- #define AR9300_GPIO_IN_VAL_S                     0
  #define AR7010_GPIO_IN_VAL                       0x0000FFFF
  #define AR7010_GPIO_IN_VAL_S                     0
  
+ #define AR_GPIO_IN                             0x404c
+ #define AR9300_GPIO_IN_VAL                       0x0001FFFF
+ #define AR9300_GPIO_IN_VAL_S                     0
  #define AR_GPIO_OE_OUT                           (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c)
  #define AR_GPIO_OE_OUT_DRV                       0x3
  #define AR_GPIO_OE_OUT_DRV_NO                    0x0
  #define AR_INTR_PRIO_ASYNC_MASK   0x40c8
  #define AR_INTR_PRIO_SYNC_MASK    0x40cc
  #define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4
 +#define AR_ENT_OTP              0x40d8
 +#define AR_ENT_OTP_CHAIN2_DISABLE               0x00020000
 +#define AR_ENT_OTP_MPSD               0x00800000
  
  #define AR_RTC_9300_PLL_DIV          0x000003ff
  #define AR_RTC_9300_PLL_DIV_S        0
  #define AR_PCU_TBTT_PROTECT        0x00200000
  #define AR_PCU_CLEAR_VMF           0x01000000
  #define AR_PCU_CLEAR_BA_VALID      0x04000000
 +#define AR_PCU_ALWAYS_PERFORM_KEYSEARCH 0x10000000
  
  #define AR_PCU_BT_ANT_PREVENT_RX   0x00100000
  #define AR_PCU_BT_ANT_PREVENT_RX_S 20
index 511dbe3caf58bdc517cdff1d8399f07bb0881997,dc7b30b170d037de1dc9b38b058458a98f8efb43..870df8c42622bab94db2aab3da880ad61381bb16
@@@ -428,7 -428,6 +428,7 @@@ static void carl9170_cancel_worker(stru
        cancel_delayed_work_sync(&ar->led_work);
  #endif /* CONFIG_CARL9170_LEDS */
        cancel_work_sync(&ar->ps_work);
 +      cancel_work_sync(&ar->ping_work);
        cancel_work_sync(&ar->ampdu_work);
  }
  
@@@ -534,21 -533,6 +534,21 @@@ void carl9170_restart(struct ar9170 *ar
         */
  }
  
 +static void carl9170_ping_work(struct work_struct *work)
 +{
 +      struct ar9170 *ar = container_of(work, struct ar9170, ping_work);
 +      int err;
 +
 +      if (!IS_STARTED(ar))
 +              return;
 +
 +      mutex_lock(&ar->mutex);
 +      err = carl9170_echo_test(ar, 0xdeadbeef);
 +      if (err)
 +              carl9170_restart(ar, CARL9170_RR_UNRESPONSIVE_DEVICE);
 +      mutex_unlock(&ar->mutex);
 +}
 +
  static int carl9170_init_interface(struct ar9170 *ar,
                                   struct ieee80211_vif *vif)
  {
@@@ -1630,7 -1614,6 +1630,7 @@@ void *carl9170_alloc(size_t priv_size
                skb_queue_head_init(&ar->tx_pending[i]);
        }
        INIT_WORK(&ar->ps_work, carl9170_ps_work);
 +      INIT_WORK(&ar->ping_work, carl9170_ping_work);
        INIT_WORK(&ar->restart_work, carl9170_restart_work);
        INIT_WORK(&ar->ampdu_work, carl9170_ampdu_work);
        INIT_DELAYED_WORK(&ar->tx_janitor, carl9170_tx_janitor);
         * supports these modes. The code which will add the
         * additional interface_modes is in fw.c.
         */
-       hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
+       hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
+                                    BIT(NL80211_IFTYPE_P2P_CLIENT);
  
        hw->flags |= IEEE80211_HW_RX_INCLUDES_FCS |
                     IEEE80211_HW_REPORTS_TX_ACK_STATUS |
@@@ -1845,7 -1829,7 +1846,7 @@@ int carl9170_register(struct ar9170 *ar
        err = carl9170_led_register(ar);
        if (err)
                goto err_unreg;
 -#endif /* CONFIG_CAR9L170_LEDS */
 +#endif /* CONFIG_CARL9170_LEDS */
  
  #ifdef CONFIG_CARL9170_WPC
        err = carl9170_register_wps_button(ar);
index aee5c9d89a144c9da093c52ad577097d6f064b42,7e6506a77bbb625a28ad0e6b41f7984607fe5f80..6cc58e052d101727c00e084667ba4527d7d74ef1
@@@ -242,11 -242,9 +242,11 @@@ static void carl9170_tx_release(struct 
                        ar->tx_ampdu_schedule = true;
  
                if (txinfo->flags & IEEE80211_TX_STAT_AMPDU) {
 -                      txinfo->status.ampdu_len = txinfo->pad[0];
 -                      txinfo->status.ampdu_ack_len = txinfo->pad[1];
 -                      txinfo->pad[0] = txinfo->pad[1] = 0;
 +                      struct _carl9170_tx_superframe *super;
 +
 +                      super = (void *)skb->data;
 +                      txinfo->status.ampdu_len = super->s.rix;
 +                      txinfo->status.ampdu_ack_len = super->s.cnt;
                } else if (txinfo->flags & IEEE80211_TX_STAT_ACK) {
                        /*
                         * drop redundant tx_status reports:
@@@ -339,8 -337,7 +339,8 @@@ static void carl9170_tx_status_process_
        u8 tid;
  
        if (!(txinfo->flags & IEEE80211_TX_CTL_AMPDU) ||
 -          txinfo->flags & IEEE80211_TX_CTL_INJECTED)
 +          txinfo->flags & IEEE80211_TX_CTL_INJECTED ||
 +         (!(super->f.mac_control & cpu_to_le16(AR9170_TX_MAC_AGGR))))
                return;
  
        tx_info = IEEE80211_SKB_CB(skb);
                sta_info->stats[tid].ampdu_ack_len++;
  
        if (super->f.mac_control & cpu_to_le16(AR9170_TX_MAC_IMM_BA)) {
 -              txinfo->pad[0] = sta_info->stats[tid].ampdu_len;
 -              txinfo->pad[1] = sta_info->stats[tid].ampdu_ack_len;
 +              super->s.rix = sta_info->stats[tid].ampdu_len;
 +              super->s.cnt = sta_info->stats[tid].ampdu_ack_len;
                txinfo->flags |= IEEE80211_TX_STAT_AMPDU;
                sta_info->stats[tid].clear = true;
        }
@@@ -527,59 -524,6 +527,59 @@@ next
        }
  }
  
 +static void carl9170_tx_ampdu_timeout(struct ar9170 *ar)
 +{
 +      struct carl9170_sta_tid *iter;
 +      struct sk_buff *skb;
 +      struct ieee80211_tx_info *txinfo;
 +      struct carl9170_tx_info *arinfo;
 +      struct _carl9170_tx_superframe *super;
 +      struct ieee80211_sta *sta;
 +      struct ieee80211_vif *vif;
 +      struct ieee80211_hdr *hdr;
 +      unsigned int vif_id;
 +
 +      rcu_read_lock();
 +      list_for_each_entry_rcu(iter, &ar->tx_ampdu_list, list) {
 +              if (iter->state < CARL9170_TID_STATE_IDLE)
 +                      continue;
 +
 +              spin_lock_bh(&iter->lock);
 +              skb = skb_peek(&iter->queue);
 +              if (!skb)
 +                      goto unlock;
 +
 +              txinfo = IEEE80211_SKB_CB(skb);
 +              arinfo = (void *)txinfo->rate_driver_data;
 +              if (time_is_after_jiffies(arinfo->timeout +
 +                  msecs_to_jiffies(CARL9170_QUEUE_TIMEOUT)))
 +                      goto unlock;
 +
 +              super = (void *) skb->data;
 +              hdr = (void *) super->frame_data;
 +
 +              vif_id = (super->s.misc & CARL9170_TX_SUPER_MISC_VIF_ID) >>
 +                       CARL9170_TX_SUPER_MISC_VIF_ID_S;
 +
 +              if (WARN_ON(vif_id >= AR9170_MAX_VIRTUAL_MAC))
 +                      goto unlock;
 +
 +              vif = rcu_dereference(ar->vif_priv[vif_id].vif);
 +              if (WARN_ON(!vif))
 +                      goto unlock;
 +
 +              sta = ieee80211_find_sta(vif, hdr->addr1);
 +              if (WARN_ON(!sta))
 +                      goto unlock;
 +
 +              ieee80211_stop_tx_ba_session(sta, iter->tid);
 +unlock:
 +              spin_unlock_bh(&iter->lock);
 +
 +      }
 +      rcu_read_unlock();
 +}
 +
  void carl9170_tx_janitor(struct work_struct *work)
  {
        struct ar9170 *ar = container_of(work, struct ar9170,
        ar->tx_janitor_last_run = jiffies;
  
        carl9170_check_queue_stop_timeout(ar);
 +      carl9170_tx_ampdu_timeout(ar);
  
        if (!atomic_read(&ar->tx_total_queued))
                return;
@@@ -867,7 -810,7 +867,7 @@@ static int carl9170_tx_prepare(struct a
  
        mac_tmp = cpu_to_le16(AR9170_TX_MAC_HW_DURATION |
                              AR9170_TX_MAC_BACKOFF);
-       mac_tmp |= cpu_to_le16((hw_queue << AR9170_TX_MAC_QOS_S) &&
+       mac_tmp |= cpu_to_le16((hw_queue << AR9170_TX_MAC_QOS_S) &
                               AR9170_TX_MAC_QOS);
  
        no_ack = !!(info->flags & IEEE80211_TX_CTL_NO_ACK);
                if (unlikely(!sta || !cvif))
                        goto err_out;
  
 -              factor = min_t(unsigned int, 1u,
 -                       info->control.sta->ht_cap.ampdu_factor);
 -
 -              density = info->control.sta->ht_cap.ampdu_density;
 +              factor = min_t(unsigned int, 1u, sta->ht_cap.ampdu_factor);
 +              density = sta->ht_cap.ampdu_density;
  
                if (density) {
                        /*
@@@ -1261,7 -1206,6 +1261,7 @@@ static void carl9170_tx(struct ar9170 *
  static bool carl9170_tx_ampdu_queue(struct ar9170 *ar,
        struct ieee80211_sta *sta, struct sk_buff *skb)
  {
 +      struct _carl9170_tx_superframe *super = (void *) skb->data;
        struct carl9170_sta_info *sta_info;
        struct carl9170_sta_tid *agg;
        struct sk_buff *iter;
@@@ -1330,7 -1274,6 +1330,7 @@@ err_unlock
  
  err_unlock_rcu:
        rcu_read_unlock();
 +      super->f.mac_control &= ~cpu_to_le16(AR9170_TX_MAC_AGGR);
        carl9170_tx_status(ar, skb, false);
        ar->tx_dropped++;
        return false;
@@@ -1359,6 -1302,9 +1359,6 @@@ int carl9170_op_tx(struct ieee80211_hw 
         */
  
        if (info->flags & IEEE80211_TX_CTL_AMPDU) {
 -              if (WARN_ON_ONCE(!sta))
 -                      goto err_free;
 -
                run = carl9170_tx_ampdu_queue(ar, sta, skb);
                if (run)
                        carl9170_tx_ampdu(ar);
index 143473c5939323c75a2a15a915bfd1df5d9f315d,fcd1bbfc632d527364b8f1fc91abd70ba3242225..6836a6dd985331d7462034b808ffcf422c6e587d
@@@ -851,10 -851,9 +851,10 @@@ struct lbs_private *lbs_add_card(void *
        priv->work_thread = create_singlethread_workqueue("lbs_worker");
        INIT_WORK(&priv->mcast_work, lbs_set_mcast_worker);
  
 -      priv->wol_criteria = 0xffffffff;
 +      priv->wol_criteria = EHS_REMOVE_WAKEUP;
        priv->wol_gpio = 0xff;
        priv->wol_gap = 20;
 +      priv->ehs_remove_supported = true;
  
        goto done;
  
@@@ -916,8 -915,6 +916,6 @@@ void lbs_remove_card(struct lbs_privat
  
        lbs_free_adapter(priv);
        lbs_cfg_free(priv);
-       priv->dev = NULL;
        free_netdev(dev);
  
        lbs_deb_leave(LBS_DEB_MAIN);
diff --combined net/mac80211/rx.c
index d83334bbb24564751e0eb6643dbbf47245837563,54fb4a0e76f03d835c6038cffeabf18874cb2d59..6289525c09985857b90c3c49930b9cd4f72bc7c4
@@@ -538,8 -538,6 +538,8 @@@ static void ieee80211_release_reorder_f
  {
        struct sk_buff *skb = tid_agg_rx->reorder_buf[index];
  
 +      lockdep_assert_held(&tid_agg_rx->reorder_lock);
 +
        if (!skb)
                goto no_frame;
  
@@@ -559,8 -557,6 +559,8 @@@ static void ieee80211_release_reorder_f
  {
        int index;
  
 +      lockdep_assert_held(&tid_agg_rx->reorder_lock);
 +
        while (seq_less(tid_agg_rx->head_seq_num, head_seq_num)) {
                index = seq_sub(tid_agg_rx->head_seq_num, tid_agg_rx->ssn) %
                                                        tid_agg_rx->buf_size;
@@@ -585,8 -581,6 +585,8 @@@ static void ieee80211_sta_reorder_relea
  {
        int index, j;
  
 +      lockdep_assert_held(&tid_agg_rx->reorder_lock);
 +
        /* release the buffer until next missing frame */
        index = seq_sub(tid_agg_rx->head_seq_num, tid_agg_rx->ssn) %
                                                tid_agg_rx->buf_size;
@@@ -689,11 -683,10 +689,11 @@@ static bool ieee80211_sta_manage_reorde
        int index;
        bool ret = true;
  
 +      spin_lock(&tid_agg_rx->reorder_lock);
 +
        buf_size = tid_agg_rx->buf_size;
        head_seq_num = tid_agg_rx->head_seq_num;
  
 -      spin_lock(&tid_agg_rx->reorder_lock);
        /* frame with out of date sequence number */
        if (seq_less(mpdu_seq_num, head_seq_num)) {
                dev_kfree_skb(skb);
@@@ -1109,6 -1102,8 +1109,6 @@@ static void ap_sta_ps_end(struct sta_in
  
        atomic_dec(&sdata->bss->num_sta_ps);
  
 -      clear_sta_flags(sta, WLAN_STA_PS_STA);
 -
  #ifdef CONFIG_MAC80211_VERBOSE_PS_DEBUG
        printk(KERN_DEBUG "%s: STA %pM aid %d exits power save mode\n",
               sdata->name, sta->sta.addr, sta->sta.aid);
@@@ -1877,8 -1872,9 +1877,8 @@@ ieee80211_rx_h_data(struct ieee80211_rx
        dev->stats.rx_packets++;
        dev->stats.rx_bytes += rx->skb->len;
  
 -      if (ieee80211_is_data(hdr->frame_control) &&
 -          !is_multicast_ether_addr(hdr->addr1) &&
 -          local->hw.conf.dynamic_ps_timeout > 0 && local->ps_sdata) {
 +      if (local->ps_sdata && local->hw.conf.dynamic_ps_timeout > 0 &&
 +          !is_multicast_ether_addr(((struct ethhdr *)rx->skb->data)->h_dest)) {
                        mod_timer(&local->dynamic_ps_timer, jiffies +
                         msecs_to_jiffies(local->hw.conf.dynamic_ps_timeout));
        }
@@@ -1927,12 -1923,9 +1927,12 @@@ ieee80211_rx_h_ctrl(struct ieee80211_rx
                        mod_timer(&tid_agg_rx->session_timer,
                                  TU_TO_EXP_TIME(tid_agg_rx->timeout));
  
 +              spin_lock(&tid_agg_rx->reorder_lock);
                /* release stored frames up to start of BAR */
                ieee80211_release_reorder_frames(hw, tid_agg_rx, start_seq_num,
                                                 frames);
 +              spin_unlock(&tid_agg_rx->reorder_lock);
 +
                kfree_skb(skb);
                return RX_QUEUED;
        }
@@@ -2254,6 -2247,10 +2254,10 @@@ ieee80211_rx_h_mgmt(struct ieee80211_rx
                break;
        case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
        case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
+               if (is_multicast_ether_addr(mgmt->da) &&
+                   !is_broadcast_ether_addr(mgmt->da))
+                       return RX_DROP_MONITOR;
                /* process only for station */
                if (sdata->vif.type != NL80211_IFTYPE_STATION)
                        return RX_DROP_MONITOR;
@@@ -2524,8 -2521,9 +2528,8 @@@ static void ieee80211_invoke_rx_handler
  }
  
  /*
 - * This function makes calls into the RX path. Therefore the
 - * caller must hold the sta_info->lock and everything has to
 - * be under rcu_read_lock protection as well.
 + * This function makes calls into the RX path, therefore
 + * it has to be invoked under RCU read lock.
   */
  void ieee80211_release_reorder_timeout(struct sta_info *sta, int tid)
  {
@@@ -2747,6 -2745,7 +2751,7 @@@ static void __ieee80211_rx_handle_packe
  
                        if (ieee80211_prepare_and_rx_handle(&rx, skb, true))
                                return;
+                       goto out;
                }
        }
  
                        return;
        }
  
+  out:
        dev_kfree_skb(skb);
  }
  
diff --combined net/mac80211/tx.c
index e69483647f33c03f9958dfaa60d3d7c1e276dd9a,df6aac523532c5d5bb8940d4d98fa91b48e0e4b2..2ba7426568252b78064eb498f5e0b46e038d2623
@@@ -622,8 -622,7 +622,8 @@@ ieee80211_tx_h_rate_ctrl(struct ieee802
                txrc.max_rate_idx = -1;
        else
                txrc.max_rate_idx = fls(txrc.rate_idx_mask) - 1;
 -      txrc.ap = tx->sdata->vif.type == NL80211_IFTYPE_AP;
 +      txrc.bss = (tx->sdata->vif.type == NL80211_IFTYPE_AP ||
 +                  tx->sdata->vif.type == NL80211_IFTYPE_ADHOC);
  
        /* set up RTS protection if desired */
        if (len > tx->local->hw.wiphy->rts_threshold) {
@@@ -1034,7 -1033,6 +1034,7 @@@ static bool __ieee80211_parse_tx_radiot
        struct ieee80211_radiotap_header *rthdr =
                (struct ieee80211_radiotap_header *) skb->data;
        struct ieee80211_supported_band *sband;
 +      bool hw_frag;
        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
        int ret = ieee80211_radiotap_iterator_init(&iterator, rthdr, skb->len,
                                                   NULL);
        info->flags |= IEEE80211_TX_INTFL_DONT_ENCRYPT;
        tx->flags &= ~IEEE80211_TX_FRAGMENTED;
  
 +      /* packet is fragmented in HW if we have a non-NULL driver callback */
 +      hw_frag = (tx->local->ops->set_frag_threshold != NULL);
 +
        /*
         * for every radiotap entry that is present
         * (ieee80211_radiotap_iterator_next returns -ENOENT when no more
                        }
                        if (*iterator.this_arg & IEEE80211_RADIOTAP_F_WEP)
                                info->flags &= ~IEEE80211_TX_INTFL_DONT_ENCRYPT;
 -                      if (*iterator.this_arg & IEEE80211_RADIOTAP_F_FRAG)
 +                      if ((*iterator.this_arg & IEEE80211_RADIOTAP_F_FRAG) &&
 +                                                              !hw_frag)
                                tx->flags |= IEEE80211_TX_FRAGMENTED;
                        break;
  
@@@ -1187,10 -1181,8 +1187,10 @@@ ieee80211_tx_prepare(struct ieee80211_s
        /*
         * Set this flag (used below to indicate "automatic fragmentation"),
         * it will be cleared/left by radiotap as desired.
 +       * Only valid when fragmentation is done by the stack.
         */
 -      tx->flags |= IEEE80211_TX_FRAGMENTED;
 +      if (!local->ops->set_frag_threshold)
 +              tx->flags |= IEEE80211_TX_FRAGMENTED;
  
        /* process and remove the injection radiotap header */
        if (unlikely(info->flags & IEEE80211_TX_INTFL_HAS_RADIOTAP)) {
@@@ -1595,7 -1587,12 +1595,12 @@@ static void ieee80211_xmit(struct ieee8
                                                list) {
                                if (!ieee80211_sdata_running(tmp_sdata))
                                        continue;
-                               if (tmp_sdata->vif.type != NL80211_IFTYPE_AP)
+                               if (tmp_sdata->vif.type ==
+                                   NL80211_IFTYPE_MONITOR ||
+                                   tmp_sdata->vif.type ==
+                                   NL80211_IFTYPE_AP_VLAN ||
+                                       tmp_sdata->vif.type ==
+                                   NL80211_IFTYPE_WDS)
                                        continue;
                                if (compare_ether_addr(tmp_sdata->vif.addr,
                                                       hdr->addr2) == 0) {
@@@ -2309,7 -2306,7 +2314,7 @@@ struct sk_buff *ieee80211_beacon_get_ti
                txrc.max_rate_idx = -1;
        else
                txrc.max_rate_idx = fls(txrc.rate_idx_mask) - 1;
 -      txrc.ap = true;
 +      txrc.bss = true;
        rate_control_get_rate(sdata, NULL, &txrc);
  
        info->control.vif = vif;