drm: vc4: Fix pixel-wrap issue with DVP teardown

Adjust the DVP enable/disable sequence to avoid a pixel getting stuck
in an internal, non resettable FIFO within PixelValve when changing
HDMI resolution.

The blank pixels features of the DVP can prevent signals back to
pixelvalve causing it to not clear the FIFO. Adjust the ordering
and timing of operations to ensure the clear signal makes it through to
pixelvalve.

Signed-off-by: Tim Gover <tim.gover@raspberrypi.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20210628130533.144617-1-maxime@cerno.tech

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 8b24755451890409eeb1787e64a6531538e54654..cbeec6a5cb906d325908c71f491a2c315c549cb6 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -605,12 +605,12 @@ static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 
        HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 
-       HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
-                  VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC);
+       HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 
-       HDMI_WRITE(HDMI_VID_CTL,
-                  HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
+       mdelay(1);
 
+       HDMI_WRITE(HDMI_VID_CTL,
+                  HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
        vc4_hdmi_disable_scrambling(encoder);
 }
 
@@ -620,12 +620,12 @@ static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
        struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
        int ret;
 
+       HDMI_WRITE(HDMI_VID_CTL,
+                  HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
+
        if (vc4_hdmi->variant->phy_disable)
                vc4_hdmi->variant->phy_disable(vc4_hdmi);
 
-       HDMI_WRITE(HDMI_VID_CTL,
-                  HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
-
        clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
        clk_disable_unprepare(vc4_hdmi->hsm_clock);
        clk_disable_unprepare(vc4_hdmi->pixel_clock);
@@ -1017,6 +1017,7 @@ static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
 
        HDMI_WRITE(HDMI_VID_CTL,
                   VC4_HD_VID_CTL_ENABLE |
+                  VC4_HD_VID_CTL_CLRRGB |
                   VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
                   VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
                   (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |