pwm: lpc18xx-sct: Test clock rate to avoid division by 0

The clk API may return 0 on clk_get_rate(), so we should check the
result before using it as a divisor.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

diff --git a/drivers/pwm/pwm-lpc18xx-sct.c b/drivers/pwm/pwm-lpc18xx-sct.c
index 9163085101bc947b4f4cb8ff2d5ae7a9b8452375..9861fed4e67d04e8d9f8f8488c7c276b3560fe7d 100644 (file)
--- a/drivers/pwm/pwm-lpc18xx-sct.c
+++ b/drivers/pwm/pwm-lpc18xx-sct.c
@@ -360,6 +360,11 @@ static int lpc18xx_pwm_probe(struct platform_device *pdev)
        }
 
        lpc18xx_pwm->clk_rate = clk_get_rate(lpc18xx_pwm->pwm_clk);
+       if (!lpc18xx_pwm->clk_rate) {
+               dev_err(&pdev->dev, "pwm clock has no frequency\n");
+               ret = -EINVAL;
+               goto disable_pwmclk;
+       }
 
        mutex_init(&lpc18xx_pwm->res_lock);
        mutex_init(&lpc18xx_pwm->period_lock);