ARM: dts: imx6qdl-icore-rqs: Add CAN nodes

Add support for can1 and can2 nodes on Engicam i.CoreM6 RQS
QDL module boards.

Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
index e97002b674c4abd48786f1cd1b89a4975c8d5a08..b6220d62f6de0f48f2ba667f237d90e987f1bcf7 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
@@ -173,6 +173,20 @@
        };
 };
 
+&can1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_can1>;
+       xceiver-supply = <&reg_3p3v>;
+       status = "okay";
+};
+
+&can2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_can2>;
+       xceiver-supply = <&reg_3p3v>;
+       status = "okay";
+};
+
 &clks {
        assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
        assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
@@ -328,6 +342,20 @@
                >;
        };
 
+       pinctrl_can1: can1grp {
+               fsl,pins = <
+                       MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
+                       MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
+               >;
+       };
+
+       pinctrl_can2: can2grp {
+               fsl,pins = <
+                       MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
+                       MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
+               >;
+       };
+
        pinctrl_i2c1: i2c1grp {
                fsl,pins = <
                        MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1