net: phy: marvell: update abilities and advertising when switching to SGMII

With some SFP modules, such as Finisar FCLF8522P2BTL, the PHY hardware
strapping defaults to 1000BaseX mode, but the kernel prefers to set them
for SGMII mode. When this happens and the PHY is soft reset, the BMSR
status register is updated, but this happens after the kernel has already
read the PHY abilities during probing. This results in support not being
detected for, and the PHY not advertising support for, 10 and 100 Mbps
modes, preventing the link from working with a non-gigabit link partner.

When the PHY is being configured for SGMII mode, call genphy_read_abilities
again in order to re-read the capabilities, and update the advertising
field accordingly.

Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 2702faf7b0f60210587af984367e6403c3ce5742..47e83c1e9051d30d98340f25606d05a598043e5c 100644 (file)
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -961,7 +961,21 @@ static int m88e1111_config_init(struct phy_device *phydev)
        if (err < 0)
                return err;
 
-       return genphy_soft_reset(phydev);
+       err = genphy_soft_reset(phydev);
+       if (err < 0)
+               return err;
+
+       if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+               /* If the HWCFG_MODE was changed from another mode (such as
+                * 1000BaseX) to SGMII, the state of the support bits may have
+                * also changed now that the PHY has been reset.
+                * Update the PHY abilities accordingly.
+                */
+               err = genphy_read_abilities(phydev);
+               linkmode_or(phydev->advertising, phydev->advertising,
+                           phydev->supported);
+       }
+       return err;
 }
 
 static int m88e1111_get_downshift(struct phy_device *phydev, u8 *data)