perf/x86/intel: Set PERF_ATTACH_SCHED_CB for large PEBS and LBR

BugLink: https://bugs.launchpad.net/bugs/1919492
[ Upstream commit afbef30149587ad46f4780b1e0cc5e219745ce90 ]

To supply a PID/TID for large PEBS, it requires flushing the PEBS buffer
in a context switch.

For normal LBRs, a context switch can flip the address space and LBR
entries are not tagged with an identifier, we need to wipe the LBR, even
for per-cpu events.

For LBR callstack, save/restore the stack is required during a context
switch.

Set PERF_ATTACH_SCHED_CB for the event with large PEBS & LBR.

Fixes: 9c964efa4330 ("perf/x86/intel: Drain the PEBS buffer during context switches")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lkml.kernel.org/r/20201130193842.10569-2-kan.liang@linux.intel.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Seth Forshee <seth.forshee@canonical.com>

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 4faaef3a8f6c43bb983759eb1a1548d56284f7b7..d3f5cf70c1a09458ce201d84b6416a736e8c3ae1 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3578,8 +3578,10 @@ static int intel_pmu_hw_config(struct perf_event *event)
                if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
                        event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
                        if (!(event->attr.sample_type &
-                             ~intel_pmu_large_pebs_flags(event)))
+                             ~intel_pmu_large_pebs_flags(event))) {
                                event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
+                               event->attach_state |= PERF_ATTACH_SCHED_CB;
+                       }
                }
                if (x86_pmu.pebs_aliases)
                        x86_pmu.pebs_aliases(event);
@@ -3592,6 +3594,7 @@ static int intel_pmu_hw_config(struct perf_event *event)
                ret = intel_pmu_setup_lbr_filter(event);
                if (ret)
                        return ret;
+               event->attach_state |= PERF_ATTACH_SCHED_CB;
 
                /*
                 * BTS is set up earlier in this path, so don't account twice