net/mlx5e: E-Switch, Add misc bit when misc fields changed for mirroring

The modified flow_context fields in FTE must be indicated in
modify_enable bitmask. Previously, the misc bit in modify_enable is
always set as source vport must be set for each rule. So, when parsing
vxlan/gre/geneve/qinq rules, this bit is not set because those are all
from the same misc fileds that source vport fields are located at, and
we don't need to set the indicator twice.

After adding per vport tables for mirroring, misc bit is not set, then
firmware syndrome happens. To fix it, set the bit wherever misc fileds
are changed. This also makes it unnecessary to check misc fields and set
the misc bit accordingly in metadata matching, so here remove it.

Besides, flow_source must be specified for uplink because firmware
will check it and some actions are only allowed for packets received
from uplink.

Fixes: 96e326878fa5 ("net/mlx5e: Eswitch, Use per vport tables for mirroring")
Signed-off-by: Jianbo Liu <jianbol@mellanox.com>
Reviewed-by: Chris Mi <chrism@mellanox.com>
Reviewed-by: Roi Dayan <roid@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c
index 951ea26d96bc3f0cc27cfb13c8a9b181e18bb64a..e472ed0eacfbc72b6e9e15a7bc7539a6bbe57df7 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c
@@ -301,6 +301,8 @@ static int mlx5e_tc_tun_parse_geneve_params(struct mlx5e_priv *priv,
                MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type, ETH_P_TEB);
        }
 
+       spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
+
        return 0;
 }
 

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_gre.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_gre.c
index 58b13192df23945394448031eb99524812333086..2805416c32a3cbfa373c0b08706d88f182ff4669 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_gre.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_gre.c
@@ -80,6 +80,8 @@ static int mlx5e_tc_tun_parse_gretap(struct mlx5e_priv *priv,
                         gre_key.key, be32_to_cpu(enc_keyid.key->keyid));
        }
 
+       spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
+
        return 0;
 }
 

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_vxlan.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_vxlan.c
index 37b176801bccbd5e700f6e2cd9630590c3edfb02..038a0f1cecec63eb3199306d75fd888bde24dd12 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_vxlan.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_vxlan.c
@@ -136,6 +136,8 @@ static int mlx5e_tc_tun_parse_vxlan(struct mlx5e_priv *priv,
        MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
                 be32_to_cpu(enc_keyid.key->keyid));
 
+       spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
+
        return 0;
 }
 

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
index cc8412151ca09ad3a100c54a3e637f90e3e46af6..fcedb5bdca9e57bda7d9c52cca8f910954ff6175 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
@@ -2356,6 +2356,7 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
                                 match.key->vlan_priority);
 
                        *match_level = MLX5_MATCH_L2;
+                       spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
                }
        }
 

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c
index 060354bb211adeaeb90c90caf9d64d3461dc8b7b..d70d6c099582cca6b6ce2cadcae68eec9da082e9 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c
@@ -259,9 +259,6 @@ mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
                         mlx5_eswitch_get_vport_metadata_mask());
 
                spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
-               misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
-               if (memchr_inv(misc, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc)))
-                       spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
        } else {
                misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
                MLX5_SET(fte_match_set_misc, misc, source_port, attr->in_rep->vport);
@@ -380,6 +377,9 @@ mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
                flow_act.modify_hdr = attr->modify_hdr;
 
        if (split) {
+               if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) &&
+                   attr->in_rep->vport == MLX5_VPORT_UPLINK)
+                       spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK;
                fdb = esw_vport_tbl_get(esw, attr);
        } else {
                if (attr->chain || attr->prio)