]> git.proxmox.com Git - mirror_ubuntu-disco-kernel.git/commitdiff
clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC
authorTakeshi Kihara <takeshi.kihara.df@renesas.com>
Fri, 28 Sep 2018 07:33:06 +0000 (16:33 +0900)
committerStefan Bader <stefan.bader@canonical.com>
Tue, 13 Aug 2019 12:11:36 +0000 (14:11 +0200)
BugLink: https://bugs.launchpad.net/bugs/1837517
[ Upstream commit b9df2ea2b8d09ad850afe4d4a0403cb23d9e0c02 ]

The clock sources of the AXI-bus clock (266.66 MHz) used for Audio-DMAC
DMA transfers are:

    Channel        R-Car H3    R-Car M3-W    R-Car M3-N    R-Car E3
    ---------------------------------------------------------------
    Audio-DMAC0    S1D2        S1D2          S1D2          S1D2
    Audio-DMAC1    S1D2        S1D2          S1D2          -

As a result, change the parent clocks of the Audio-DMAC{0,1} module
clocks on R-Car H3, R-Car M3-W, and R-Car M3-N to S1D2, and change the
parent clock of the Audio-DMAC0 module on R-Car E3 to S1D2.

NOTE: This information will be reflected in a future revision of the
      R-Car Gen3 Hardware Manual.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update R-Car D3, RZ/G2M, and RZ/G2E]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Khalid Elmously <khalid.elmously@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>
drivers/clk/renesas/r8a774a1-cpg-mssr.c
drivers/clk/renesas/r8a774c0-cpg-mssr.c
drivers/clk/renesas/r8a7795-cpg-mssr.c
drivers/clk/renesas/r8a7796-cpg-mssr.c
drivers/clk/renesas/r8a77965-cpg-mssr.c
drivers/clk/renesas/r8a77990-cpg-mssr.c
drivers/clk/renesas/r8a77995-cpg-mssr.c

index ddde2a7a242739d1a619412566255c89755fda28..904d4d4ebcad5820242bedf86d5c0df4515f87c1 100644 (file)
@@ -142,8 +142,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
        DEF_MOD("rwdt",                  402,   R8A774A1_CLK_R),
        DEF_MOD("intc-ex",               407,   R8A774A1_CLK_CP),
        DEF_MOD("intc-ap",               408,   R8A774A1_CLK_S0D3),
-       DEF_MOD("audmac1",               501,   R8A774A1_CLK_S0D3),
-       DEF_MOD("audmac0",               502,   R8A774A1_CLK_S0D3),
+       DEF_MOD("audmac1",               501,   R8A774A1_CLK_S1D2),
+       DEF_MOD("audmac0",               502,   R8A774A1_CLK_S1D2),
        DEF_MOD("hscif4",                516,   R8A774A1_CLK_S3D1),
        DEF_MOD("hscif3",                517,   R8A774A1_CLK_S3D1),
        DEF_MOD("hscif2",                518,   R8A774A1_CLK_S3D1),
index 10b96895d45217a29e80eff494d18ec9ea234595..4a0525425c1610ab77ca4273acf3e06e1631d750 100644 (file)
@@ -149,7 +149,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
        DEF_MOD("intc-ex",               407,   R8A774C0_CLK_CP),
        DEF_MOD("intc-ap",               408,   R8A774C0_CLK_S0D3),
 
-       DEF_MOD("audmac0",               502,   R8A774C0_CLK_S3D4),
+       DEF_MOD("audmac0",               502,   R8A774C0_CLK_S1D2),
        DEF_MOD("hscif4",                516,   R8A774C0_CLK_S3D1C),
        DEF_MOD("hscif3",                517,   R8A774C0_CLK_S3D1C),
        DEF_MOD("hscif2",                518,   R8A774C0_CLK_S3D1C),
index eade38e9ed36bc57dfb1c21041a1139f7a2c6a00..0825cd0ff28669907155445633226957711563c5 100644 (file)
@@ -153,8 +153,8 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
        DEF_MOD("rwdt",                  402,   R8A7795_CLK_R),
        DEF_MOD("intc-ex",               407,   R8A7795_CLK_CP),
        DEF_MOD("intc-ap",               408,   R8A7795_CLK_S0D3),
-       DEF_MOD("audmac1",               501,   R8A7795_CLK_S0D3),
-       DEF_MOD("audmac0",               502,   R8A7795_CLK_S0D3),
+       DEF_MOD("audmac1",               501,   R8A7795_CLK_S1D2),
+       DEF_MOD("audmac0",               502,   R8A7795_CLK_S1D2),
        DEF_MOD("drif7",                 508,   R8A7795_CLK_S3D2),
        DEF_MOD("drif6",                 509,   R8A7795_CLK_S3D2),
        DEF_MOD("drif5",                 510,   R8A7795_CLK_S3D2),
index 654f3ea88f335917fe062ea8e5b955dc5d9a9d34..997cd956f12bc32a4cc9343bb7c17043f32e26c4 100644 (file)
@@ -146,8 +146,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
        DEF_MOD("rwdt",                  402,   R8A7796_CLK_R),
        DEF_MOD("intc-ex",               407,   R8A7796_CLK_CP),
        DEF_MOD("intc-ap",               408,   R8A7796_CLK_S0D3),
-       DEF_MOD("audmac1",               501,   R8A7796_CLK_S0D3),
-       DEF_MOD("audmac0",               502,   R8A7796_CLK_S0D3),
+       DEF_MOD("audmac1",               501,   R8A7796_CLK_S1D2),
+       DEF_MOD("audmac0",               502,   R8A7796_CLK_S1D2),
        DEF_MOD("drif7",                 508,   R8A7796_CLK_S3D2),
        DEF_MOD("drif6",                 509,   R8A7796_CLK_S3D2),
        DEF_MOD("drif5",                 510,   R8A7796_CLK_S3D2),
index 13d1f88be04a57af7d6648fb3a23a191a95d9f15..afc9c72fa0940b45dcb9cf0f9d28ec040f418bc0 100644 (file)
@@ -146,8 +146,8 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
        DEF_MOD("intc-ex",              407,    R8A77965_CLK_CP),
        DEF_MOD("intc-ap",              408,    R8A77965_CLK_S0D3),
 
-       DEF_MOD("audmac1",              501,    R8A77965_CLK_S0D3),
-       DEF_MOD("audmac0",              502,    R8A77965_CLK_S0D3),
+       DEF_MOD("audmac1",              501,    R8A77965_CLK_S1D2),
+       DEF_MOD("audmac0",              502,    R8A77965_CLK_S1D2),
        DEF_MOD("drif7",                508,    R8A77965_CLK_S3D2),
        DEF_MOD("drif6",                509,    R8A77965_CLK_S3D2),
        DEF_MOD("drif5",                510,    R8A77965_CLK_S3D2),
index 9a278c75c918cfa8cc095163510b407883b919d0..03f445d47ef692eae0b46661682ab40ee5045a12 100644 (file)
@@ -152,7 +152,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
        DEF_MOD("intc-ex",               407,   R8A77990_CLK_CP),
        DEF_MOD("intc-ap",               408,   R8A77990_CLK_S0D3),
 
-       DEF_MOD("audmac0",               502,   R8A77990_CLK_S3D4),
+       DEF_MOD("audmac0",               502,   R8A77990_CLK_S1D2),
        DEF_MOD("drif7",                 508,   R8A77990_CLK_S3D2),
        DEF_MOD("drif6",                 509,   R8A77990_CLK_S3D2),
        DEF_MOD("drif5",                 510,   R8A77990_CLK_S3D2),
index eee3874865a95b1a2007a6c1ccb7244a5e030c0f..68707277b17b42c4267ff893ede58dd00b0021fd 100644 (file)
@@ -133,7 +133,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
        DEF_MOD("rwdt",                  402,   R8A77995_CLK_R),
        DEF_MOD("intc-ex",               407,   R8A77995_CLK_CP),
        DEF_MOD("intc-ap",               408,   R8A77995_CLK_S1D2),
-       DEF_MOD("audmac0",               502,   R8A77995_CLK_S3D1),
+       DEF_MOD("audmac0",               502,   R8A77995_CLK_S1D2),
        DEF_MOD("hscif3",                517,   R8A77995_CLK_S3D1C),
        DEF_MOD("hscif0",                520,   R8A77995_CLK_S3D1C),
        DEF_MOD("thermal",               522,   R8A77995_CLK_CP),