drm/amd/display: Move DCN314 DOMAIN power control to DMCUB

BugLink: https://bugs.launchpad.net/bugs/2009358
commit e383b12709e32d6494c948422070c2464b637e44 upstream.

[Why]
DOMAIN power gating control is now required to be done via firmware
due to interlock with other power features. This is to avoid
intermittent issues in the LB memories.

[How]
If the firmware supports the command then use the new firmware as
the sequence can avoid potential display corruption issues.

The command will be ignored on firmware that does not support DOMAIN
power control and the pipes will remain always on - frequent PG cycling
can cause the issue to occur on the old sequence, so we should avoid it.

Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: "Limonciello, Mario" <Mario.Limonciello@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Andrea Righi <andrea.righi@canonical.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
index a0741794db62aa77af7a3be1c8c75485e149a0e7..8e824dc81dede1e4922f6ce2d61240679a3c3eab 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
@@ -391,3 +391,27 @@ void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
                pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
                                pix_per_cycle);
 }
+
+void dcn314_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
+{
+       struct dc_context *ctx = hws->ctx;
+       union dmub_rb_cmd cmd;
+
+       if (hws->ctx->dc->debug.disable_hubp_power_gate)
+               return;
+
+       PERF_TRACE();
+
+       memset(&cmd, 0, sizeof(cmd));
+       cmd.domain_control.header.type = DMUB_CMD__VBIOS;
+       cmd.domain_control.header.sub_type = DMUB_CMD__VBIOS_DOMAIN_CONTROL;
+       cmd.domain_control.header.payload_bytes = sizeof(cmd.domain_control.data);
+       cmd.domain_control.data.inst = hubp_inst;
+       cmd.domain_control.data.power_gate = !power_on;
+
+       dc_dmub_srv_cmd_queue(ctx->dmub_srv, &cmd);
+       dc_dmub_srv_cmd_execute(ctx->dmub_srv);
+       dc_dmub_srv_wait_idle(ctx->dmub_srv);
+
+       PERF_TRACE();
+}

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
index 244280298212c5c97bd9147c4fd51e9650515665..c419d3dbdfee6d6e04d953d3681b6d0c177cd2dc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
@@ -41,4 +41,6 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig
 
 void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
 
+void dcn314_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
+
 #endif /* __DC_HWSS_DCN314_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
index 31feb4b0edee9f7666c479db669600e3ffa130e2..25f345ff6c8f0a6c10a9e3960ba83dd20d8c13e0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
@@ -137,7 +137,7 @@ static const struct hwseq_private_funcs dcn314_private_funcs = {
        .plane_atomic_disable = dcn20_plane_atomic_disable,
        .plane_atomic_power_down = dcn10_plane_atomic_power_down,
        .enable_power_gating_plane = dcn314_enable_power_gating_plane,
-       .hubp_pg_control = dcn31_hubp_pg_control,
+       .hubp_pg_control = dcn314_hubp_pg_control,
        .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
        .update_odm = dcn314_update_odm,
        .dsc_pg_control = dcn314_dsc_pg_control,

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 33907feefebbdcc2ac145b160a5b7d8aafcd1e37..8fea8e42cc174d2c02cef706a60d3e55ca6fae26 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -457,6 +457,10 @@ enum dmub_cmd_vbios_type {
         * Query DP alt status on a transmitter.
         */
        DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT  = 26,
+       /**
+        * Controls domain power gating
+        */
+       DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28,
 };
 
 //==============================================================================
@@ -1204,6 +1208,23 @@ struct dmub_rb_cmd_dig1_transmitter_control {
        union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */
 };
 
+/**
+ * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control
+ */
+struct dmub_rb_cmd_domain_control_data {
+       uint8_t inst : 6; /**< DOMAIN instance to control */
+       uint8_t power_gate : 1; /**< 1=power gate, 0=power up */
+       uint8_t reserved[3]; /**< Reserved for future use */
+};
+
+/**
+ * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating
+ */
+struct dmub_rb_cmd_domain_control {
+       struct dmub_cmd_header header; /**< header */
+       struct dmub_rb_cmd_domain_control_data data; /**< payload */
+};
+
 /**
  * DPIA tunnel command parameters.
  */
@@ -3231,6 +3252,10 @@ union dmub_rb_cmd {
         * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command.
         */
        struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
+       /**
+        * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command.
+        */
+       struct dmub_rb_cmd_domain_control domain_control;
        /**
         * Definition of a DMUB_CMD__PSR_SET_VERSION command.
         */