Merge branches 'clk-vc5', 'clk-silabs', 'clk-aspeed', 'clk-qoriq' and 'clk-rohm'...

 - Support crystal load capacitance for Versaclock VC5
 - Add a "skip recall" DT binding for Silicon Labs' si570 to avoid glitches at boot

* clk-vc5:
  clk: vc5: Add support for optional load capacitance
  dt-bindings: clk: versaclock5: Add optional load capacitance property

* clk-silabs:
  clk: si570: Skip NVM to RAM recall operation if an optional property is set
  dt-bindings: clock: si570: Add 'silabs,skip-recall' property

* clk-aspeed:
  clk: aspeed: Fix APLL calculate formula from ast2600-A2

* clk-qoriq:
  clk: qoriq: use macros to generate pll_mask

* clk-rohm:
  clk: BD718x7: Do not depend on parent driver data