ARM: dts: bcm2837: Add the missing L1/L2 cache information

BugLink: https://bugs.launchpad.net/bugs/1969110
[ Upstream commit bdf8762da268d2a34abf517c36528413906e9cd5 ]

This patch fixes the kernel warning
"cacheinfo: Unable to detect cache hierarchy for CPU 0"
for the bcm2837 on newer kernel versions.

Signed-off-by: Richard Schleich <rs@noreya.tech>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
[florian: Align and remove comments matching property values]
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
(cherry picked from commit 35a2aeb70fe62b28cbe2e0c823835936c299ea13)
Signed-off-by: Paolo Pisati <paolo.pisati@canonical.com>

diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi
index 0199ec98cd61690ad964c1bbe782fcf64583b236..5dbdebc4625946a266d2c3f1719256086d5a2a59 100644 (file)
--- a/arch/arm/boot/dts/bcm2837.dtsi
+++ b/arch/arm/boot/dts/bcm2837.dtsi
@@ -40,12 +40,26 @@
                #size-cells = <0>;
                enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
 
+               /* Source for d/i-cache-line-size and d/i-cache-sets
+                * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
+                * /about-the-l1-memory-system?lang=en
+                *
+                * Source for d/i-cache-size
+                * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks
+                */
                cpu0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        reg = <0>;
                        enable-method = "spin-table";
                        cpu-release-addr = <0x0 0x000000d8>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+                       next-level-cache = <&l2>;
                };
 
                cpu1: cpu@1 {
@@ -54,6 +68,13 @@
                        reg = <1>;
                        enable-method = "spin-table";
                        cpu-release-addr = <0x0 0x000000e0>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+                       next-level-cache = <&l2>;
                };
 
                cpu2: cpu@2 {
@@ -62,6 +83,13 @@
                        reg = <2>;
                        enable-method = "spin-table";
                        cpu-release-addr = <0x0 0x000000e8>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+                       next-level-cache = <&l2>;
                };
 
                cpu3: cpu@3 {
@@ -70,6 +98,27 @@
                        reg = <3>;
                        enable-method = "spin-table";
                        cpu-release-addr = <0x0 0x000000f0>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+                       next-level-cache = <&l2>;
+               };
+
+               /* Source for cache-line-size + cache-sets
+                * https://developer.arm.com/documentation/ddi0500
+                * /e/level-2-memory-system/about-the-l2-memory-system?lang=en
+                * Source for cache-size
+                * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf
+                */
+               l2: l2-cache0 {
+                       compatible = "cache";
+                       cache-size = <0x80000>;
+                       cache-line-size = <64>;
+                       cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
+                       cache-level = <2>;
                };
        };
 };