PCI: keystone: Allow AM654 PCIe Endpoint to raise MSI-X interrupt

AM654 PCIe EP controller has MSI-X capability register and has the
ability to raise MSI-X interrupt. Add support in pci-keystone.c
for PCIe endpoint controller in AM654 to raise MSI-X interrupts.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index c8c702c494a2da14a1f044bd1504cea9a3fede60..790679fdfa488cf727c7c8c14dc334fac16062a4 100644 (file)
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -959,6 +959,9 @@ static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
        case PCI_EPC_IRQ_MSI:
                dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
                break;
+       case PCI_EPC_IRQ_MSIX:
+               dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
+               break;
        default:
                dev_err(pci->dev, "UNKNOWN IRQ type\n");
                return -EINVAL;
@@ -970,7 +973,7 @@ static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
 static const struct pci_epc_features ks_pcie_am654_epc_features = {
        .linkup_notifier = false,
        .msi_capable = true,
-       .msix_capable = false,
+       .msix_capable = true,
        .reserved_bar = 1 << BAR_0 | 1 << BAR_1,
        .bar_fixed_64bit = 1 << BAR_0,
        .bar_fixed_size[2] = SZ_1M,