ARM: dts: socfpga: fix register entry for timer3 on Arria10

BugLink: https://bugs.launchpad.net/bugs/1896824
[ Upstream commit 0ff5a4812be4ebd4782bbb555d369636eea164f7 ]

Fixes the register address for the timer3 entry on Arria10.

Fixes: 475dc86d08de4 ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: William Breathitt Gray <william.gray@canonical.com>

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 906bfb580e9e7122918f3ab52bdd465697300488..f261a334407101084aad8e89d1eedabcac15020a 100644 (file)
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -819,7 +819,7 @@
                timer3: timer3@ffd00100 {
                        compatible = "snps,dw-apb-timer";
                        interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
-                       reg = <0xffd01000 0x100>;
+                       reg = <0xffd00100 0x100>;
                        clocks = <&l4_sys_free_clk>;
                        clock-names = "timer";
                        resets = <&rst L4SYSTIMER1_RESET>;