Pull first round of updates for meson clocks from Jerome Brunet:
- Remove legacy register access (finish moving to syscon)
- Clean up configuration flags
- Add axg PCIe clocks
- Add GEN CLK on gxbb, gxl and axg
- Remove clk_audio_divider driver
- Add axg audio clock controller
* tag 'meson-clk-4.19-1' of https://github.com/BayLibre/clk-meson:
clk: meson: add gen_clk
clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition
clk: meson-axg: add clocks required by pcie driver
clk: meson: remove unused clk-audio-divider driver
clk: meson: stop rate propagation for audio clocks
clk: meson: axg: add the audio clock controller driver
clk: meson: add axg audio sclk divider driver
clk: meson: add triple phase clock driver
clk: meson: add clk-phase clock driver
clk: meson: clean-up meson clock configuration
clk: meson: remove obsolete register access
clk: meson: expose GEN_CLK clkid
clk: meson-axg: add pcie and mipi clock bindings
dt-bindings: clock: add meson axg audio clock controller bindings
clk: meson: audio-divider is one based
clk: add duty cycle support
clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL