/* add bo's to gpu's ring, and kick gpu: */
void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
{
- struct drm_device *dev = gpu->dev;
- struct msm_drm_private *priv = dev->dev_private;
struct msm_ringbuffer *ring = submit->ring;
unsigned long flags;
submit->seqno = submit->hw_fence->seqno;
- msm_rd_dump_submit(priv->rd, submit, NULL);
-
update_sw_cntrs(gpu);
/*
bool open;
- /* current submit to read out: */
- struct msm_gem_submit *submit;
-
/* fifo access is synchronized on the producer side by
- * gpu->lock held by submit code (otherwise we could
- * end up w/ cmds logged in different order than they
- * were executed). And read_lock synchronizes the reads
+ * write_lock. And read_lock synchronizes the reads
*/
- struct mutex read_lock;
+ struct mutex read_lock, write_lock;
wait_queue_head_t fifo_event;
struct circ_buf fifo;
return;
mutex_destroy(&rd->read_lock);
+ mutex_destroy(&rd->write_lock);
kfree(rd);
}
rd->fifo.buf = rd->buf;
mutex_init(&rd->read_lock);
+ mutex_init(&rd->write_lock);
init_waitqueue_head(&rd->fifo_event);
if (!(submit->bos[idx].flags & MSM_SUBMIT_BO_READ))
return;
- msm_gem_lock(&obj->base);
buf = msm_gem_get_vaddr_active(&obj->base);
if (IS_ERR(buf))
- goto out_unlock;
+ return;
buf += offset;
rd_write_section(rd, RD_BUFFER_CONTENTS, buf, size);
msm_gem_put_vaddr_locked(&obj->base);
-
-out_unlock:
- msm_gem_unlock(&obj->base);
}
/* called under gpu->lock */
if (!rd->open)
return;
- /* writing into fifo is serialized by caller, and
- * rd->read_lock is used to serialize the reads
- */
- WARN_ON(!mutex_is_locked(&submit->gpu->lock));
+ mutex_lock(&rd->write_lock);
if (fmt) {
va_list args;
break;
}
}
+
+ mutex_unlock(&rd->write_lock);
}
#endif