drm/amdgpu/psp11: simplify the ucode register logic

Split it between navi10 and newer and everything before
navi10.

Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 759b2768c51ced757f1409ddb8cc467782c8845d..61744e2d16fbc5cb82a4b44ddfb45d72f5840ac1 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -534,7 +534,7 @@ psp_v11_0_sram_map(struct amdgpu_device *adev,
 
        case AMDGPU_UCODE_ID_RLC_G:
                *sram_offset = 0x2000;
-               if (adev->asic_type != CHIP_NAVI10) {
+               if (adev->asic_type < CHIP_NAVI10) {
                        *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
                        *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
                } else {
@@ -545,7 +545,7 @@ psp_v11_0_sram_map(struct amdgpu_device *adev,
 
        case AMDGPU_UCODE_ID_SDMA0:
                *sram_offset = 0x0;
-               if (adev->asic_type != CHIP_NAVI10) {
+               if (adev->asic_type < CHIP_NAVI10) {
                        *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
                        *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
                } else {