drm/amd/powerplay: fix sw SMU wrong UVD/VCE powergate setting

The UVD/VCE bits are set wrongly. This causes the UVD/VCE clocks
are not brought back correctly on needed.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 940b519686d58b0a94eb404a6184f5c2ecafe32b..d2eeb624048478b24433295562d63907a7e96b51 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1835,24 +1835,24 @@ static int smu_v11_0_update_od8_settings(struct smu_context *smu,
 
 static int smu_v11_0_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
 {
-       if (!smu_feature_is_supported(smu, FEATURE_DPM_VCE_BIT))
+       if (!smu_feature_is_supported(smu, FEATURE_DPM_UVD_BIT))
                return 0;
 
-       if (enable == smu_feature_is_enabled(smu, FEATURE_DPM_VCE_BIT))
+       if (enable == smu_feature_is_enabled(smu, FEATURE_DPM_UVD_BIT))
                return 0;
 
-       return smu_feature_set_enabled(smu, FEATURE_DPM_VCE_BIT, enable);
+       return smu_feature_set_enabled(smu, FEATURE_DPM_UVD_BIT, enable);
 }
 
 static int smu_v11_0_dpm_set_vce_enable(struct smu_context *smu, bool enable)
 {
-       if (!smu_feature_is_supported(smu, FEATURE_DPM_UVD_BIT))
+       if (!smu_feature_is_supported(smu, FEATURE_DPM_VCE_BIT))
                return 0;
 
-       if (enable == smu_feature_is_enabled(smu, FEATURE_DPM_UVD_BIT))
+       if (enable == smu_feature_is_enabled(smu, FEATURE_DPM_VCE_BIT))
                return 0;
 
-       return smu_feature_set_enabled(smu, FEATURE_DPM_UVD_BIT, enable);
+       return smu_feature_set_enabled(smu, FEATURE_DPM_VCE_BIT, enable);
 }
 
 static int smu_v11_0_get_current_rpm(struct smu_context *smu,