--- /dev/null
+/*
+ * iwMMXt micro operations for XScale.
+ *
+ * Copyright (c) 2007 OpenedHand, Ltd.
+ * Written by Andrzej Zaborowski <andrew@openedhand.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#define M1 env->iwmmxt.regs[PARAM1]
+
+/* iwMMXt macros extracted from GNU gdb. */
+
+/* Set the SIMD wCASF flags for 8, 16, 32 or 64-bit operations. */
+#define SIMD8_SET( v, n, b) ((v != 0) << ((((b) + 1) * 4) + (n)))
+#define SIMD16_SET(v, n, h) ((v != 0) << ((((h) + 1) * 8) + (n)))
+#define SIMD32_SET(v, n, w) ((v != 0) << ((((w) + 1) * 16) + (n)))
+#define SIMD64_SET(v, n) ((v != 0) << (32 + (n)))
+/* Flags to pass as "n" above. */
+#define SIMD_NBIT -1
+#define SIMD_ZBIT -2
+#define SIMD_CBIT -3
+#define SIMD_VBIT -4
+/* Various status bit macros. */
+#define NBIT8(x) ((x) & 0x80)
+#define NBIT16(x) ((x) & 0x8000)
+#define NBIT32(x) ((x) & 0x80000000)
+#define NBIT64(x) ((x) & 0x8000000000000000ULL)
+#define ZBIT8(x) (((x) & 0xff) == 0)
+#define ZBIT16(x) (((x) & 0xffff) == 0)
+#define ZBIT32(x) (((x) & 0xffffffff) == 0)
+#define ZBIT64(x) (x == 0)
+/* Sign extension macros. */
+#define EXTEND8H(a) ((uint16_t) (int8_t) (a))
+#define EXTEND8(a) ((uint32_t) (int8_t) (a))
+#define EXTEND16(a) ((uint32_t) (int16_t) (a))
+#define EXTEND16S(a) ((int32_t) (int16_t) (a))
+#define EXTEND32(a) ((uint64_t) (int32_t) (a))
+
+void OPPROTO op_iwmmxt_movl_T0_T1_wRn(void)
+{
+ T0 = M1 & ~(uint32_t) 0;
+ T1 = M1 >> 32;
+}
+
+void OPPROTO op_iwmmxt_movl_wRn_T0_T1(void)
+{
+ M1 = ((uint64_t) T1 << 32) | T0;
+}
+
+void OPPROTO op_iwmmxt_movq_M0_wRn(void)
+{
+ M0 = M1;
+}
+
+void OPPROTO op_iwmmxt_orq_M0_wRn(void)
+{
+ M0 |= M1;
+}
+
+void OPPROTO op_iwmmxt_andq_M0_wRn(void)
+{
+ M0 &= M1;
+}
+
+void OPPROTO op_iwmmxt_xorq_M0_wRn(void)
+{
+ M0 ^= M1;
+}
+
+void OPPROTO op_iwmmxt_maddsq_M0_wRn(void)
+{
+ M0 = ((
+ EXTEND16S((M0 >> 0) & 0xffff) * EXTEND16S((M1 >> 0) & 0xffff) +
+ EXTEND16S((M0 >> 16) & 0xffff) * EXTEND16S((M1 >> 16) & 0xffff)
+ ) & 0xffffffff) | ((uint64_t) (
+ EXTEND16S((M0 >> 32) & 0xffff) * EXTEND16S((M1 >> 32) & 0xffff) +
+ EXTEND16S((M0 >> 48) & 0xffff) * EXTEND16S((M1 >> 48) & 0xffff)
+ ) << 32);
+}
+
+void OPPROTO op_iwmmxt_madduq_M0_wRn(void)
+{
+ M0 = ((
+ ((M0 >> 0) & 0xffff) * ((M1 >> 0) & 0xffff) +
+ ((M0 >> 16) & 0xffff) * ((M1 >> 16) & 0xffff)
+ ) & 0xffffffff) | ((
+ ((M0 >> 32) & 0xffff) * ((M1 >> 32) & 0xffff) +
+ ((M0 >> 48) & 0xffff) * ((M1 >> 48) & 0xffff)
+ ) << 32);
+}
+
+void OPPROTO op_iwmmxt_sadb_M0_wRn(void)
+{
+#define abs(x) (((x) >= 0) ? x : -x)
+#define SADB(SHR) abs((int) ((M0 >> SHR) & 0xff) - (int) ((M1 >> SHR) & 0xff))
+ M0 =
+ SADB(0) + SADB(8) + SADB(16) + SADB(24) +
+ SADB(32) + SADB(40) + SADB(48) + SADB(56);
+#undef SADB
+}
+
+void OPPROTO op_iwmmxt_sadw_M0_wRn(void)
+{
+#define SADW(SHR) \
+ abs((int) ((M0 >> SHR) & 0xffff) - (int) ((M1 >> SHR) & 0xffff))
+ M0 = SADW(0) + SADW(16) + SADW(32) + SADW(48);
+#undef SADW
+}
+
+void OPPROTO op_iwmmxt_addl_M0_wRn(void)
+{
+ M0 += env->iwmmxt.regs[PARAM1] & 0xffffffff;
+}
+
+void OPPROTO op_iwmmxt_mulsw_M0_wRn(void)
+{
+#define MULS(SHR) ((uint64_t) ((( \
+ EXTEND16S((M0 >> SHR) & 0xffff) * EXTEND16S((M1 >> SHR) & 0xffff) \
+ ) >> PARAM2) & 0xffff) << SHR)
+ M0 = MULS(0) | MULS(16) | MULS(32) | MULS(48);
+#undef MULS
+}
+
+void OPPROTO op_iwmmxt_muluw_M0_wRn(void)
+{
+#define MULU(SHR) ((uint64_t) ((( \
+ ((M0 >> SHR) & 0xffff) * ((M1 >> SHR) & 0xffff) \
+ ) >> PARAM2) & 0xffff) << SHR)
+ M0 = MULU(0) | MULU(16) | MULU(32) | MULU(48);
+#undef MULU
+}
+
+void OPPROTO op_iwmmxt_macsw_M0_wRn(void)
+{
+#define MACS(SHR) ( \
+ EXTEND16((M0 >> SHR) & 0xffff) * EXTEND16S((M1 >> SHR) & 0xffff))
+ M0 = (int64_t) (MACS(0) + MACS(16) + MACS(32) + MACS(48));
+#undef MACS
+}
+
+void OPPROTO op_iwmmxt_macuw_M0_wRn(void)
+{
+#define MACU(SHR) ( \
+ (uint32_t) ((M0 >> SHR) & 0xffff) * \
+ (uint32_t) ((M1 >> SHR) & 0xffff))
+ M0 = MACU(0) + MACU(16) + MACU(32) + MACU(48);
+#undef MACU
+}
+
+void OPPROTO op_iwmmxt_addsq_M0_wRn(void)
+{
+ M0 = (int64_t) M0 + (int64_t) M1;
+}
+
+void OPPROTO op_iwmmxt_adduq_M0_wRn(void)
+{
+ M0 += M1;
+}
+
+void OPPROTO op_iwmmxt_movq_wRn_M0(void)
+{
+ M1 = M0;
+}
+
+void OPPROTO op_iwmmxt_movl_wCx_T0(void)
+{
+ env->iwmmxt.cregs[PARAM1] = T0;
+}
+
+void OPPROTO op_iwmmxt_movl_T0_wCx(void)
+{
+ T0 = env->iwmmxt.cregs[PARAM1];
+}
+
+void OPPROTO op_iwmmxt_movl_T1_wCx(void)
+{
+ T1 = env->iwmmxt.cregs[PARAM1];
+}
+
+void OPPROTO op_iwmmxt_set_mup(void)
+{
+ env->iwmmxt.cregs[ARM_IWMMXT_wCon] |= 2;
+}
+
+void OPPROTO op_iwmmxt_set_cup(void)
+{
+ env->iwmmxt.cregs[ARM_IWMMXT_wCon] |= 1;
+}
+
+void OPPROTO op_iwmmxt_setpsr_nz(void)
+{
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
+ SIMD64_SET((M0 == 0), SIMD_ZBIT) |
+ SIMD64_SET((M0 & (1ULL << 63)), SIMD_NBIT);
+}
+
+void OPPROTO op_iwmmxt_negq_M0(void)
+{
+ M0 = ~M0;
+}
+
+#define NZBIT8(x, i) \
+ SIMD8_SET(NBIT8((x) & 0xff), SIMD_NBIT, i) | \
+ SIMD8_SET(ZBIT8((x) & 0xff), SIMD_ZBIT, i)
+#define NZBIT16(x, i) \
+ SIMD16_SET(NBIT16((x) & 0xffff), SIMD_NBIT, i) | \
+ SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)
+#define NZBIT32(x, i) \
+ SIMD32_SET(NBIT32((x) & 0xffffffff), SIMD_NBIT, i) | \
+ SIMD32_SET(ZBIT32((x) & 0xffffffff), SIMD_ZBIT, i)
+#define NZBIT64(x) \
+ SIMD64_SET(NBIT64(x), SIMD_NBIT) | \
+ SIMD64_SET(ZBIT64(x), SIMD_ZBIT)
+#define IWMMXT_OP_UNPACK(S, SH0, SH1, SH2, SH3) \
+void OPPROTO glue(op_iwmmxt_unpack, glue(S, b_M0_wRn))(void) \
+{ \
+ M0 = \
+ (((M0 >> SH0) & 0xff) << 0) | (((M1 >> SH0) & 0xff) << 8) | \
+ (((M0 >> SH1) & 0xff) << 16) | (((M1 >> SH1) & 0xff) << 24) | \
+ (((M0 >> SH2) & 0xff) << 32) | (((M1 >> SH2) & 0xff) << 40) | \
+ (((M0 >> SH3) & 0xff) << 48) | (((M1 >> SH3) & 0xff) << 56); \
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
+ NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) | \
+ NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) | \
+ NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) | \
+ NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7); \
+} \
+void OPPROTO glue(op_iwmmxt_unpack, glue(S, w_M0_wRn))(void) \
+{ \
+ M0 = \
+ (((M0 >> SH0) & 0xffff) << 0) | \
+ (((M1 >> SH0) & 0xffff) << 16) | \
+ (((M0 >> SH2) & 0xffff) << 32) | \
+ (((M1 >> SH2) & 0xffff) << 48); \
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
+ NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 16, 1) | \
+ NZBIT8(M0 >> 32, 2) | NZBIT8(M0 >> 48, 3); \
+} \
+void OPPROTO glue(op_iwmmxt_unpack, glue(S, l_M0_wRn))(void) \
+{ \
+ M0 = \
+ (((M0 >> SH0) & 0xffffffff) << 0) | \
+ (((M1 >> SH0) & 0xffffffff) << 32); \
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
+ NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \
+} \
+void OPPROTO glue(op_iwmmxt_unpack, glue(S, ub_M0))(void) \
+{ \
+ M0 = \
+ (((M0 >> SH0) & 0xff) << 0) | \
+ (((M0 >> SH1) & 0xff) << 16) | \
+ (((M0 >> SH2) & 0xff) << 32) | \
+ (((M0 >> SH3) & 0xff) << 48); \
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
+ NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | \
+ NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); \
+} \
+void OPPROTO glue(op_iwmmxt_unpack, glue(S, uw_M0))(void) \
+{ \
+ M0 = \
+ (((M0 >> SH0) & 0xffff) << 0) | \
+ (((M0 >> SH2) & 0xffff) << 32); \
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
+ NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \
+} \
+void OPPROTO glue(op_iwmmxt_unpack, glue(S, ul_M0))(void) \
+{ \
+ M0 = (((M0 >> SH0) & 0xffffffff) << 0); \
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0 >> 0); \
+} \
+void OPPROTO glue(op_iwmmxt_unpack, glue(S, sb_M0))(void) \
+{ \
+ M0 = \
+ ((uint64_t) EXTEND8H((M0 >> SH0) & 0xff) << 0) | \
+ ((uint64_t) EXTEND8H((M0 >> SH1) & 0xff) << 16) | \
+ ((uint64_t) EXTEND8H((M0 >> SH2) & 0xff) << 32) | \
+ ((uint64_t) EXTEND8H((M0 >> SH3) & 0xff) << 48); \
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
+ NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | \
+ NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); \
+} \
+void OPPROTO glue(op_iwmmxt_unpack, glue(S, sw_M0))(void) \
+{ \
+ M0 = \
+ ((uint64_t) EXTEND16((M0 >> SH0) & 0xffff) << 0) | \
+ ((uint64_t) EXTEND16((M0 >> SH2) & 0xffff) << 32); \
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
+ NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \
+} \
+void OPPROTO glue(op_iwmmxt_unpack, glue(S, sl_M0))(void) \
+{ \
+ M0 = EXTEND32((M0 >> SH0) & 0xffffffff); \
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0 >> 0); \
+}
+IWMMXT_OP_UNPACK(l, 0, 8, 16, 24)
+IWMMXT_OP_UNPACK(h, 32, 40, 48, 56)
+
+#define IWMMXT_OP_CMP(SUFF, Tb, Tw, Tl, O) \
+void OPPROTO glue(op_iwmmxt_, glue(SUFF, b_M0_wRn))(void) \
+{ \
+ M0 = \
+ CMP(0, Tb, O, 0xff) | CMP(8, Tb, O, 0xff) | \
+ CMP(16, Tb, O, 0xff) | CMP(24, Tb, O, 0xff) | \
+ CMP(32, Tb, O, 0xff) | CMP(40, Tb, O, 0xff) | \
+ CMP(48, Tb, O, 0xff) | CMP(56, Tb, O, 0xff); \
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
+ NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) | \
+ NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) | \
+ NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) | \
+ NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7); \
+} \
+void OPPROTO glue(op_iwmmxt_, glue(SUFF, w_M0_wRn))(void) \
+{ \
+ M0 = CMP(0, Tw, O, 0xffff) | CMP(16, Tw, O, 0xffff) | \
+ CMP(32, Tw, O, 0xffff) | CMP(48, Tw, O, 0xffff); \
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
+ NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) | \
+ NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3); \
+} \
+void OPPROTO glue(op_iwmmxt_, glue(SUFF, l_M0_wRn))(void) \
+{ \
+ M0 = CMP(0, Tl, O, 0xffffffff) | \
+ CMP(32, Tl, O, 0xffffffff); \
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = \
+ NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1); \
+}
+#define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((M0 >> SHR) & MASK) OPER \
+ (TYPE) ((M1 >> SHR) & MASK)) ? (uint64_t) MASK : 0) << SHR)
+IWMMXT_OP_CMP(cmpeq, uint8_t, uint16_t, uint32_t, ==)
+IWMMXT_OP_CMP(cmpgts, int8_t, int16_t, int32_t, >)
+IWMMXT_OP_CMP(cmpgtu, uint8_t, uint16_t, uint32_t, >)
+#undef CMP
+#define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((M0 >> SHR) & MASK) OPER \
+ (TYPE) ((M1 >> SHR) & MASK)) ? M0 : M1) & ((uint64_t) MASK << SHR))
+IWMMXT_OP_CMP(mins, int8_t, int16_t, int32_t, <)
+IWMMXT_OP_CMP(minu, uint8_t, uint16_t, uint32_t, <)
+IWMMXT_OP_CMP(maxs, int8_t, int16_t, int32_t, >)
+IWMMXT_OP_CMP(maxu, uint8_t, uint16_t, uint32_t, >)
+#undef CMP
+#define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((M0 >> SHR) & MASK) \
+ OPER (TYPE) ((M1 >> SHR) & MASK)) & MASK) << SHR)
+IWMMXT_OP_CMP(subn, uint8_t, uint16_t, uint32_t, -)
+IWMMXT_OP_CMP(addn, uint8_t, uint16_t, uint32_t, +)
+#undef CMP
+/* TODO Signed- and Unsigned-Saturation */
+#define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((M0 >> SHR) & MASK) \
+ OPER (TYPE) ((M1 >> SHR) & MASK)) & MASK) << SHR)
+IWMMXT_OP_CMP(subu, uint8_t, uint16_t, uint32_t, -)
+IWMMXT_OP_CMP(addu, uint8_t, uint16_t, uint32_t, +)
+IWMMXT_OP_CMP(subs, int8_t, int16_t, int32_t, -)
+IWMMXT_OP_CMP(adds, int8_t, int16_t, int32_t, +)
+#undef CMP
+#undef IWMMXT_OP_CMP
+
+void OPPROTO op_iwmmxt_avgb_M0_wRn(void)
+{
+#define AVGB(SHR) ((( \
+ ((M0 >> SHR) & 0xff) + ((M1 >> SHR) & 0xff) + PARAM2) >> 1) << SHR)
+ M0 =
+ AVGB(0) | AVGB(8) | AVGB(16) | AVGB(24) |
+ AVGB(32) | AVGB(40) | AVGB(48) | AVGB(56);
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
+ SIMD8_SET(ZBIT8((M0 >> 0) & 0xff), SIMD_ZBIT, 0) |
+ SIMD8_SET(ZBIT8((M0 >> 8) & 0xff), SIMD_ZBIT, 1) |
+ SIMD8_SET(ZBIT8((M0 >> 16) & 0xff), SIMD_ZBIT, 2) |
+ SIMD8_SET(ZBIT8((M0 >> 24) & 0xff), SIMD_ZBIT, 3) |
+ SIMD8_SET(ZBIT8((M0 >> 32) & 0xff), SIMD_ZBIT, 4) |
+ SIMD8_SET(ZBIT8((M0 >> 40) & 0xff), SIMD_ZBIT, 5) |
+ SIMD8_SET(ZBIT8((M0 >> 48) & 0xff), SIMD_ZBIT, 6) |
+ SIMD8_SET(ZBIT8((M0 >> 56) & 0xff), SIMD_ZBIT, 7);
+#undef AVGB
+}
+
+void OPPROTO op_iwmmxt_avgw_M0_wRn(void)
+{
+#define AVGW(SHR) ((( \
+ ((M0 >> SHR) & 0xffff) + ((M1 >> SHR) & 0xffff) + PARAM2) >> 1) << SHR)
+ M0 = AVGW(0) | AVGW(16) | AVGW(32) | AVGW(48);
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
+ SIMD16_SET(ZBIT16((M0 >> 0) & 0xffff), SIMD_ZBIT, 0) |
+ SIMD16_SET(ZBIT16((M0 >> 16) & 0xffff), SIMD_ZBIT, 1) |
+ SIMD16_SET(ZBIT16((M0 >> 32) & 0xffff), SIMD_ZBIT, 2) |
+ SIMD16_SET(ZBIT16((M0 >> 48) & 0xffff), SIMD_ZBIT, 3);
+#undef AVGW
+}
+
+void OPPROTO op_iwmmxt_msadb_M0_wRn(void)
+{
+ M0 = ((((M0 >> 0) & 0xffff) * ((M1 >> 0) & 0xffff) +
+ ((M0 >> 16) & 0xffff) * ((M1 >> 16) & 0xffff)) & 0xffffffff) |
+ ((((M0 >> 32) & 0xffff) * ((M1 >> 32) & 0xffff) +
+ ((M0 >> 48) & 0xffff) * ((M1 >> 48) & 0xffff)) << 32);
+}
+
+void OPPROTO op_iwmmxt_align_M0_T0_wRn(void)
+{
+ M0 >>= T0 << 3;
+ M0 |= M1 << (64 - (T0 << 3));
+}
+
+void OPPROTO op_iwmmxt_insr_M0_T0_T1(void)
+{
+ M0 &= ~((uint64_t) T1 << PARAM1);
+ M0 |= (uint64_t) (T0 & T1) << PARAM1;
+}
+
+void OPPROTO op_iwmmxt_extrsb_T0_M0(void)
+{
+ T0 = EXTEND8((M0 >> PARAM1) & 0xff);
+}
+
+void OPPROTO op_iwmmxt_extrsw_T0_M0(void)
+{
+ T0 = EXTEND16((M0 >> PARAM1) & 0xffff);
+}
+
+void OPPROTO op_iwmmxt_extru_T0_M0_T1(void)
+{
+ T0 = (M0 >> PARAM1) & T1;
+}
+
+void OPPROTO op_iwmmxt_bcstb_M0_T0(void)
+{
+ T0 &= 0xff;
+ M0 =
+ ((uint64_t) T0 << 0) | ((uint64_t) T0 << 8) |
+ ((uint64_t) T0 << 16) | ((uint64_t) T0 << 24) |
+ ((uint64_t) T0 << 32) | ((uint64_t) T0 << 40) |
+ ((uint64_t) T0 << 48) | ((uint64_t) T0 << 56);
+}
+
+void OPPROTO op_iwmmxt_bcstw_M0_T0(void)
+{
+ T0 &= 0xffff;
+ M0 =
+ ((uint64_t) T0 << 0) | ((uint64_t) T0 << 16) |
+ ((uint64_t) T0 << 32) | ((uint64_t) T0 << 48);
+}
+
+void OPPROTO op_iwmmxt_bcstl_M0_T0(void)
+{
+ M0 = ((uint64_t) T0 << 0) | ((uint64_t) T0 << 32);
+}
+
+void OPPROTO op_iwmmxt_addcb_M0(void)
+{
+ M0 =
+ ((M0 >> 0) & 0xff) + ((M0 >> 8) & 0xff) +
+ ((M0 >> 16) & 0xff) + ((M0 >> 24) & 0xff) +
+ ((M0 >> 32) & 0xff) + ((M0 >> 40) & 0xff) +
+ ((M0 >> 48) & 0xff) + ((M0 >> 56) & 0xff);
+}
+
+void OPPROTO op_iwmmxt_addcw_M0(void)
+{
+ M0 =
+ ((M0 >> 0) & 0xffff) + ((M0 >> 16) & 0xffff) +
+ ((M0 >> 32) & 0xffff) + ((M0 >> 48) & 0xffff);
+}
+
+void OPPROTO op_iwmmxt_addcl_M0(void)
+{
+ M0 = (M0 & 0xffffffff) + (M0 >> 32);
+}
+
+void OPPROTO op_iwmmxt_msbb_T0_M0(void)
+{
+ T0 =
+ ((M0 >> 7) & 0x01) | ((M0 >> 14) & 0x02) |
+ ((M0 >> 21) & 0x04) | ((M0 >> 28) & 0x08) |
+ ((M0 >> 35) & 0x10) | ((M0 >> 42) & 0x20) |
+ ((M0 >> 49) & 0x40) | ((M0 >> 56) & 0x80);
+}
+
+void OPPROTO op_iwmmxt_msbw_T0_M0(void)
+{
+ T0 =
+ ((M0 >> 15) & 0x01) | ((M0 >> 30) & 0x02) |
+ ((M0 >> 45) & 0x04) | ((M0 >> 52) & 0x08);
+}
+
+void OPPROTO op_iwmmxt_msbl_T0_M0(void)
+{
+ T0 = ((M0 >> 31) & 0x01) | ((M0 >> 62) & 0x02);
+}
+
+void OPPROTO op_iwmmxt_srlw_M0_T0(void)
+{
+ M0 =
+ (((M0 & (0xffffll << 0)) >> T0) & (0xffffll << 0)) |
+ (((M0 & (0xffffll << 16)) >> T0) & (0xffffll << 16)) |
+ (((M0 & (0xffffll << 32)) >> T0) & (0xffffll << 32)) |
+ (((M0 & (0xffffll << 48)) >> T0) & (0xffffll << 48));
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
+ NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |
+ NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);
+}
+
+void OPPROTO op_iwmmxt_srll_M0_T0(void)
+{
+ M0 =
+ ((M0 & (0xffffffffll << 0)) >> T0) |
+ ((M0 >> T0) & (0xffffffffll << 32));
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
+ NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);
+}
+
+void OPPROTO op_iwmmxt_srlq_M0_T0(void)
+{
+ M0 >>= T0;
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);
+}
+
+void OPPROTO op_iwmmxt_sllw_M0_T0(void)
+{
+ M0 =
+ (((M0 & (0xffffll << 0)) << T0) & (0xffffll << 0)) |
+ (((M0 & (0xffffll << 16)) << T0) & (0xffffll << 16)) |
+ (((M0 & (0xffffll << 32)) << T0) & (0xffffll << 32)) |
+ (((M0 & (0xffffll << 48)) << T0) & (0xffffll << 48));
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
+ NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |
+ NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);
+}
+
+void OPPROTO op_iwmmxt_slll_M0_T0(void)
+{
+ M0 =
+ ((M0 << T0) & (0xffffffffll << 0)) |
+ ((M0 & (0xffffffffll << 32)) << T0);
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
+ NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);
+}
+
+void OPPROTO op_iwmmxt_sllq_M0_T0(void)
+{
+ M0 <<= T0;
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);
+}
+
+void OPPROTO op_iwmmxt_sraw_M0_T0(void)
+{
+ M0 =
+ ((uint64_t) ((EXTEND16(M0 >> 0) >> T0) & 0xffff) << 0) |
+ ((uint64_t) ((EXTEND16(M0 >> 16) >> T0) & 0xffff) << 16) |
+ ((uint64_t) ((EXTEND16(M0 >> 32) >> T0) & 0xffff) << 32) |
+ ((uint64_t) ((EXTEND16(M0 >> 48) >> T0) & 0xffff) << 48);
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
+ NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |
+ NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);
+}
+
+void OPPROTO op_iwmmxt_sral_M0_T0(void)
+{
+ M0 =
+ (((EXTEND32(M0 >> 0) >> T0) & 0xffffffff) << 0) |
+ (((EXTEND32(M0 >> 32) >> T0) & 0xffffffff) << 32);
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
+ NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);
+}
+
+void OPPROTO op_iwmmxt_sraq_M0_T0(void)
+{
+ M0 = (int64_t) M0 >> T0;
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);
+}
+
+void OPPROTO op_iwmmxt_rorw_M0_T0(void)
+{
+ M0 =
+ ((((M0 & (0xffffll << 0)) >> T0) |
+ ((M0 & (0xffffll << 0)) << (16 - T0))) & (0xffffll << 0)) |
+ ((((M0 & (0xffffll << 16)) >> T0) |
+ ((M0 & (0xffffll << 16)) << (16 - T0))) & (0xffffll << 16)) |
+ ((((M0 & (0xffffll << 32)) >> T0) |
+ ((M0 & (0xffffll << 32)) << (16 - T0))) & (0xffffll << 32)) |
+ ((((M0 & (0xffffll << 48)) >> T0) |
+ ((M0 & (0xffffll << 48)) << (16 - T0))) & (0xffffll << 48));
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
+ NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |
+ NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);
+}
+
+void OPPROTO op_iwmmxt_rorl_M0_T0(void)
+{
+ M0 =
+ ((M0 & (0xffffffffll << 0)) >> T0) |
+ ((M0 >> T0) & (0xffffffffll << 32)) |
+ ((M0 << (32 - T0)) & (0xffffffffll << 0)) |
+ ((M0 & (0xffffffffll << 32)) << (32 - T0));
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
+ NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);
+}
+
+void OPPROTO op_iwmmxt_rorq_M0_T0(void)
+{
+ M0 = (M0 >> T0) | (M0 << (64 - T0));
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);
+}
+
+void OPPROTO op_iwmmxt_shufh_M0_T0(void)
+{
+ M0 =
+ (((M0 >> ((T0 << 4) & 0x30)) & 0xffff) << 0) |
+ (((M0 >> ((T0 << 2) & 0x30)) & 0xffff) << 16) |
+ (((M0 >> ((T0 << 0) & 0x30)) & 0xffff) << 32) |
+ (((M0 >> ((T0 >> 2) & 0x30)) & 0xffff) << 48);
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
+ NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |
+ NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);
+}
+
+/* TODO: Unsigned-Saturation */
+void OPPROTO op_iwmmxt_packuw_M0_wRn(void)
+{
+ M0 =
+ (((M0 >> 0) & 0xff) << 0) | (((M0 >> 16) & 0xff) << 8) |
+ (((M0 >> 32) & 0xff) << 16) | (((M0 >> 48) & 0xff) << 24) |
+ (((M1 >> 0) & 0xff) << 32) | (((M1 >> 16) & 0xff) << 40) |
+ (((M1 >> 32) & 0xff) << 48) | (((M1 >> 48) & 0xff) << 56);
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
+ NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) |
+ NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) |
+ NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) |
+ NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7);
+}
+
+void OPPROTO op_iwmmxt_packul_M0_wRn(void)
+{
+ M0 =
+ (((M0 >> 0) & 0xffff) << 0) | (((M0 >> 32) & 0xffff) << 16) |
+ (((M1 >> 0) & 0xffff) << 32) | (((M1 >> 32) & 0xffff) << 48);
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
+ NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |
+ NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);
+}
+
+void OPPROTO op_iwmmxt_packuq_M0_wRn(void)
+{
+ M0 = (M0 & 0xffffffff) | ((M1 & 0xffffffff) << 32);
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
+ NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);
+}
+
+/* TODO: Signed-Saturation */
+void OPPROTO op_iwmmxt_packsw_M0_wRn(void)
+{
+ M0 =
+ (((M0 >> 0) & 0xff) << 0) | (((M0 >> 16) & 0xff) << 8) |
+ (((M0 >> 32) & 0xff) << 16) | (((M0 >> 48) & 0xff) << 24) |
+ (((M1 >> 0) & 0xff) << 32) | (((M1 >> 16) & 0xff) << 40) |
+ (((M1 >> 32) & 0xff) << 48) | (((M1 >> 48) & 0xff) << 56);
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
+ NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) |
+ NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) |
+ NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) |
+ NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7);
+}
+
+void OPPROTO op_iwmmxt_packsl_M0_wRn(void)
+{
+ M0 =
+ (((M0 >> 0) & 0xffff) << 0) | (((M0 >> 32) & 0xffff) << 16) |
+ (((M1 >> 0) & 0xffff) << 32) | (((M1 >> 32) & 0xffff) << 48);
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
+ NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |
+ NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);
+}
+
+void OPPROTO op_iwmmxt_packsq_M0_wRn(void)
+{
+ M0 = (M0 & 0xffffffff) | ((M1 & 0xffffffff) << 32);
+ env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
+ NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);
+}
+
+void OPPROTO op_iwmmxt_muladdsl_M0_T0_T1(void)
+{
+ M0 += (int32_t) EXTEND32(T0) * (int32_t) EXTEND32(T1);
+}
+
+void OPPROTO op_iwmmxt_muladdsw_M0_T0_T1(void)
+{
+ M0 += EXTEND32(EXTEND16S((T0 >> 0) & 0xffff) *
+ EXTEND16S((T1 >> 0) & 0xffff));
+ M0 += EXTEND32(EXTEND16S((T0 >> 16) & 0xffff) *
+ EXTEND16S((T1 >> 16) & 0xffff));
+}
+
+void OPPROTO op_iwmmxt_muladdswl_M0_T0_T1(void)
+{
+ M0 += EXTEND32(EXTEND16S(T0 & 0xffff) *
+ EXTEND16S(T1 & 0xffff));
+}
*
* Copyright (c) 2003 Fabrice Bellard
* Copyright (c) 2005 CodeSourcery, LLC
+ * Copyright (c) 2007 OpenedHand, Ltd.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
gen_op_vfp_setreg_F0s(vfp_reg_offset(dp, reg));
}
+#define ARM_CP_RW_BIT (1 << 20)
+
+static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn)
+{
+ int rd;
+ uint32_t offset;
+
+ rd = (insn >> 16) & 0xf;
+ gen_movl_T1_reg(s, rd);
+
+ offset = (insn & 0xff) << ((insn >> 7) & 2);
+ if (insn & (1 << 24)) {
+ /* Pre indexed */
+ if (insn & (1 << 23))
+ gen_op_addl_T1_im(offset);
+ else
+ gen_op_addl_T1_im(-offset);
+
+ if (insn & (1 << 21))
+ gen_movl_reg_T1(s, rd);
+ } else if (insn & (1 << 21)) {
+ /* Post indexed */
+ if (insn & (1 << 23))
+ gen_op_movl_T0_im(offset);
+ else
+ gen_op_movl_T0_im(- offset);
+ gen_op_addl_T0_T1();
+ gen_movl_reg_T0(s, rd);
+ } else if (!(insn & (1 << 23)))
+ return 1;
+ return 0;
+}
+
+static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask)
+{
+ int rd = (insn >> 0) & 0xf;
+
+ if (insn & (1 << 8))
+ if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3)
+ return 1;
+ else
+ gen_op_iwmmxt_movl_T0_wCx(rd);
+ else
+ gen_op_iwmmxt_movl_T0_T1_wRn(rd);
+
+ gen_op_movl_T1_im(mask);
+ gen_op_andl_T0_T1();
+ return 0;
+}
+
+/* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
+ (ie. an undefined instruction). */
+static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
+{
+ int rd, wrd;
+ int rdhi, rdlo, rd0, rd1, i;
+
+ if ((insn & 0x0e000e00) == 0x0c000000) {
+ if ((insn & 0x0fe00ff0) == 0x0c400000) {
+ wrd = insn & 0xf;
+ rdlo = (insn >> 12) & 0xf;
+ rdhi = (insn >> 16) & 0xf;
+ if (insn & ARM_CP_RW_BIT) { /* TMRRC */
+ gen_op_iwmmxt_movl_T0_T1_wRn(wrd);
+ gen_movl_reg_T0(s, rdlo);
+ gen_movl_reg_T1(s, rdhi);
+ } else { /* TMCRR */
+ gen_movl_T0_reg(s, rdlo);
+ gen_movl_T1_reg(s, rdhi);
+ gen_op_iwmmxt_movl_wRn_T0_T1(wrd);
+ gen_op_iwmmxt_set_mup();
+ }
+ return 0;
+ }
+
+ wrd = (insn >> 12) & 0xf;
+ if (gen_iwmmxt_address(s, insn))
+ return 1;
+ if (insn & ARM_CP_RW_BIT) {
+ if ((insn >> 28) == 0xf) { /* WLDRW wCx */
+ gen_ldst(ldl, s);
+ gen_op_iwmmxt_movl_wCx_T0(wrd);
+ } else {
+ if (insn & (1 << 8))
+ if (insn & (1 << 22)) /* WLDRD */
+ gen_ldst(iwmmxt_ldq, s);
+ else /* WLDRW wRd */
+ gen_ldst(iwmmxt_ldl, s);
+ else
+ if (insn & (1 << 22)) /* WLDRH */
+ gen_ldst(iwmmxt_ldw, s);
+ else /* WLDRB */
+ gen_ldst(iwmmxt_ldb, s);
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ }
+ } else {
+ if ((insn >> 28) == 0xf) { /* WSTRW wCx */
+ gen_op_iwmmxt_movl_T0_wCx(wrd);
+ gen_ldst(stl, s);
+ } else {
+ gen_op_iwmmxt_movq_M0_wRn(wrd);
+ if (insn & (1 << 8))
+ if (insn & (1 << 22)) /* WSTRD */
+ gen_ldst(iwmmxt_stq, s);
+ else /* WSTRW wRd */
+ gen_ldst(iwmmxt_stl, s);
+ else
+ if (insn & (1 << 22)) /* WSTRH */
+ gen_ldst(iwmmxt_ldw, s);
+ else /* WSTRB */
+ gen_ldst(iwmmxt_stb, s);
+ }
+ }
+ return 0;
+ }
+
+ if ((insn & 0x0f000000) != 0x0e000000)
+ return 1;
+
+ switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
+ case 0x000: /* WOR */
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 0) & 0xf;
+ rd1 = (insn >> 16) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ gen_op_iwmmxt_orq_M0_wRn(rd1);
+ gen_op_iwmmxt_setpsr_nz();
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ gen_op_iwmmxt_set_cup();
+ break;
+ case 0x011: /* TMCR */
+ if (insn & 0xf)
+ return 1;
+ rd = (insn >> 12) & 0xf;
+ wrd = (insn >> 16) & 0xf;
+ switch (wrd) {
+ case ARM_IWMMXT_wCID:
+ case ARM_IWMMXT_wCASF:
+ break;
+ case ARM_IWMMXT_wCon:
+ gen_op_iwmmxt_set_cup();
+ /* Fall through. */
+ case ARM_IWMMXT_wCSSF:
+ gen_op_iwmmxt_movl_T0_wCx(wrd);
+ gen_movl_T1_reg(s, rd);
+ gen_op_bicl_T0_T1();
+ gen_op_iwmmxt_movl_wCx_T0(wrd);
+ break;
+ case ARM_IWMMXT_wCGR0:
+ case ARM_IWMMXT_wCGR1:
+ case ARM_IWMMXT_wCGR2:
+ case ARM_IWMMXT_wCGR3:
+ gen_op_iwmmxt_set_cup();
+ gen_movl_reg_T0(s, rd);
+ gen_op_iwmmxt_movl_wCx_T0(wrd);
+ break;
+ default:
+ return 1;
+ }
+ break;
+ case 0x100: /* WXOR */
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 0) & 0xf;
+ rd1 = (insn >> 16) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ gen_op_iwmmxt_xorq_M0_wRn(rd1);
+ gen_op_iwmmxt_setpsr_nz();
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ gen_op_iwmmxt_set_cup();
+ break;
+ case 0x111: /* TMRC */
+ if (insn & 0xf)
+ return 1;
+ rd = (insn >> 12) & 0xf;
+ wrd = (insn >> 16) & 0xf;
+ gen_op_iwmmxt_movl_T0_wCx(wrd);
+ gen_movl_reg_T0(s, rd);
+ break;
+ case 0x300: /* WANDN */
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 0) & 0xf;
+ rd1 = (insn >> 16) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ gen_op_iwmmxt_negq_M0();
+ gen_op_iwmmxt_andq_M0_wRn(rd1);
+ gen_op_iwmmxt_setpsr_nz();
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ gen_op_iwmmxt_set_cup();
+ break;
+ case 0x200: /* WAND */
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 0) & 0xf;
+ rd1 = (insn >> 16) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ gen_op_iwmmxt_andq_M0_wRn(rd1);
+ gen_op_iwmmxt_setpsr_nz();
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ gen_op_iwmmxt_set_cup();
+ break;
+ case 0x810: case 0xa10: /* WMADD */
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 0) & 0xf;
+ rd1 = (insn >> 16) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_maddsq_M0_wRn(rd1);
+ else
+ gen_op_iwmmxt_madduq_M0_wRn(rd1);
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ break;
+ case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ rd1 = (insn >> 0) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ switch ((insn >> 22) & 3) {
+ case 0:
+ gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
+ break;
+ case 1:
+ gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
+ break;
+ case 2:
+ gen_op_iwmmxt_unpackll_M0_wRn(rd1);
+ break;
+ case 3:
+ return 1;
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ gen_op_iwmmxt_set_cup();
+ break;
+ case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ rd1 = (insn >> 0) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ switch ((insn >> 22) & 3) {
+ case 0:
+ gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
+ break;
+ case 1:
+ gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
+ break;
+ case 2:
+ gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
+ break;
+ case 3:
+ return 1;
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ gen_op_iwmmxt_set_cup();
+ break;
+ case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ rd1 = (insn >> 0) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ if (insn & (1 << 22))
+ gen_op_iwmmxt_sadw_M0_wRn(rd1);
+ else
+ gen_op_iwmmxt_sadb_M0_wRn(rd1);
+ if (!(insn & (1 << 20)))
+ gen_op_iwmmxt_addl_M0_wRn(wrd);
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ break;
+ case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ rd1 = (insn >> 0) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_mulsw_M0_wRn(rd1, (insn & (1 << 20)) ? 16 : 0);
+ else
+ gen_op_iwmmxt_muluw_M0_wRn(rd1, (insn & (1 << 20)) ? 16 : 0);
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ break;
+ case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ rd1 = (insn >> 0) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_macsw_M0_wRn(rd1);
+ else
+ gen_op_iwmmxt_macuw_M0_wRn(rd1);
+ if (!(insn & (1 << 20))) {
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_addsq_M0_wRn(wrd);
+ else
+ gen_op_iwmmxt_adduq_M0_wRn(wrd);
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ break;
+ case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ rd1 = (insn >> 0) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ switch ((insn >> 22) & 3) {
+ case 0:
+ gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
+ break;
+ case 1:
+ gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
+ break;
+ case 2:
+ gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
+ break;
+ case 3:
+ return 1;
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ gen_op_iwmmxt_set_cup();
+ break;
+ case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ rd1 = (insn >> 0) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ if (insn & (1 << 22))
+ gen_op_iwmmxt_avgw_M0_wRn(rd1, (insn >> 20) & 1);
+ else
+ gen_op_iwmmxt_avgb_M0_wRn(rd1, (insn >> 20) & 1);
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ gen_op_iwmmxt_set_cup();
+ break;
+ case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ rd1 = (insn >> 0) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ gen_op_iwmmxt_movl_T0_wCx(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
+ gen_op_movl_T1_im(7);
+ gen_op_andl_T0_T1();
+ gen_op_iwmmxt_align_M0_T0_wRn(rd1);
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ break;
+ case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
+ rd = (insn >> 12) & 0xf;
+ wrd = (insn >> 16) & 0xf;
+ gen_movl_T0_reg(s, rd);
+ gen_op_iwmmxt_movq_M0_wRn(wrd);
+ switch ((insn >> 6) & 3) {
+ case 0:
+ gen_op_movl_T1_im(0xff);
+ gen_op_iwmmxt_insr_M0_T0_T1((insn & 7) << 3);
+ break;
+ case 1:
+ gen_op_movl_T1_im(0xffff);
+ gen_op_iwmmxt_insr_M0_T0_T1((insn & 3) << 4);
+ break;
+ case 2:
+ gen_op_movl_T1_im(0xffffffff);
+ gen_op_iwmmxt_insr_M0_T0_T1((insn & 1) << 5);
+ break;
+ case 3:
+ return 1;
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ break;
+ case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
+ rd = (insn >> 12) & 0xf;
+ wrd = (insn >> 16) & 0xf;
+ if (rd == 15)
+ return 1;
+ gen_op_iwmmxt_movq_M0_wRn(wrd);
+ switch ((insn >> 22) & 3) {
+ case 0:
+ if (insn & 8)
+ gen_op_iwmmxt_extrsb_T0_M0((insn & 7) << 3);
+ else {
+ gen_op_movl_T1_im(0xff);
+ gen_op_iwmmxt_extru_T0_M0_T1((insn & 7) << 3);
+ }
+ break;
+ case 1:
+ if (insn & 8)
+ gen_op_iwmmxt_extrsw_T0_M0((insn & 3) << 4);
+ else {
+ gen_op_movl_T1_im(0xffff);
+ gen_op_iwmmxt_extru_T0_M0_T1((insn & 3) << 4);
+ }
+ break;
+ case 2:
+ gen_op_movl_T1_im(0xffffffff);
+ gen_op_iwmmxt_extru_T0_M0_T1((insn & 1) << 5);
+ break;
+ case 3:
+ return 1;
+ }
+ gen_op_movl_reg_TN[0][rd]();
+ break;
+ case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
+ if ((insn & 0x000ff008) != 0x0003f000)
+ return 1;
+ gen_op_iwmmxt_movl_T1_wCx(ARM_IWMMXT_wCASF);
+ switch ((insn >> 22) & 3) {
+ case 0:
+ gen_op_shrl_T1_im(((insn & 7) << 2) + 0);
+ break;
+ case 1:
+ gen_op_shrl_T1_im(((insn & 3) << 3) + 4);
+ break;
+ case 2:
+ gen_op_shrl_T1_im(((insn & 1) << 4) + 12);
+ break;
+ case 3:
+ return 1;
+ }
+ gen_op_shll_T1_im(28);
+ gen_op_movl_T0_T1();
+ gen_op_movl_cpsr_T0(0xf0000000);
+ break;
+ case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
+ rd = (insn >> 12) & 0xf;
+ wrd = (insn >> 16) & 0xf;
+ gen_movl_T0_reg(s, rd);
+ switch ((insn >> 6) & 3) {
+ case 0:
+ gen_op_iwmmxt_bcstb_M0_T0();
+ break;
+ case 1:
+ gen_op_iwmmxt_bcstw_M0_T0();
+ break;
+ case 2:
+ gen_op_iwmmxt_bcstl_M0_T0();
+ break;
+ case 3:
+ return 1;
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ break;
+ case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
+ if ((insn & 0x000ff00f) != 0x0003f000)
+ return 1;
+ gen_op_iwmmxt_movl_T1_wCx(ARM_IWMMXT_wCASF);
+ switch ((insn >> 22) & 3) {
+ case 0:
+ for (i = 0; i < 7; i ++) {
+ gen_op_shll_T1_im(4);
+ gen_op_andl_T0_T1();
+ }
+ break;
+ case 1:
+ for (i = 0; i < 3; i ++) {
+ gen_op_shll_T1_im(8);
+ gen_op_andl_T0_T1();
+ }
+ break;
+ case 2:
+ gen_op_shll_T1_im(16);
+ gen_op_andl_T0_T1();
+ break;
+ case 3:
+ return 1;
+ }
+ gen_op_movl_cpsr_T0(0xf0000000);
+ break;
+ case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ switch ((insn >> 22) & 3) {
+ case 0:
+ gen_op_iwmmxt_addcb_M0();
+ break;
+ case 1:
+ gen_op_iwmmxt_addcw_M0();
+ break;
+ case 2:
+ gen_op_iwmmxt_addcl_M0();
+ break;
+ case 3:
+ return 1;
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ break;
+ case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
+ if ((insn & 0x000ff00f) != 0x0003f000)
+ return 1;
+ gen_op_iwmmxt_movl_T1_wCx(ARM_IWMMXT_wCASF);
+ switch ((insn >> 22) & 3) {
+ case 0:
+ for (i = 0; i < 7; i ++) {
+ gen_op_shll_T1_im(4);
+ gen_op_orl_T0_T1();
+ }
+ break;
+ case 1:
+ for (i = 0; i < 3; i ++) {
+ gen_op_shll_T1_im(8);
+ gen_op_orl_T0_T1();
+ }
+ break;
+ case 2:
+ gen_op_shll_T1_im(16);
+ gen_op_orl_T0_T1();
+ break;
+ case 3:
+ return 1;
+ }
+ gen_op_movl_T1_im(0xf0000000);
+ gen_op_andl_T0_T1();
+ gen_op_movl_cpsr_T0(0xf0000000);
+ break;
+ case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
+ rd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ if ((insn & 0xf) != 0)
+ return 1;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ switch ((insn >> 22) & 3) {
+ case 0:
+ gen_op_iwmmxt_msbb_T0_M0();
+ break;
+ case 1:
+ gen_op_iwmmxt_msbw_T0_M0();
+ break;
+ case 2:
+ gen_op_iwmmxt_msbl_T0_M0();
+ break;
+ case 3:
+ return 1;
+ }
+ gen_movl_reg_T0(s, rd);
+ break;
+ case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
+ case 0x906: case 0xb06: case 0xd06: case 0xf06:
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ rd1 = (insn >> 0) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ switch ((insn >> 22) & 3) {
+ case 0:
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
+ else
+ gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
+ break;
+ case 1:
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
+ else
+ gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
+ break;
+ case 2:
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
+ else
+ gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
+ break;
+ case 3:
+ return 1;
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ gen_op_iwmmxt_set_cup();
+ break;
+ case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
+ case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ switch ((insn >> 22) & 3) {
+ case 0:
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_unpacklsb_M0();
+ else
+ gen_op_iwmmxt_unpacklub_M0();
+ break;
+ case 1:
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_unpacklsw_M0();
+ else
+ gen_op_iwmmxt_unpackluw_M0();
+ break;
+ case 2:
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_unpacklsl_M0();
+ else
+ gen_op_iwmmxt_unpacklul_M0();
+ break;
+ case 3:
+ return 1;
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ gen_op_iwmmxt_set_cup();
+ break;
+ case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
+ case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ switch ((insn >> 22) & 3) {
+ case 0:
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_unpackhsb_M0();
+ else
+ gen_op_iwmmxt_unpackhub_M0();
+ break;
+ case 1:
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_unpackhsw_M0();
+ else
+ gen_op_iwmmxt_unpackhuw_M0();
+ break;
+ case 2:
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_unpackhsl_M0();
+ else
+ gen_op_iwmmxt_unpackhul_M0();
+ break;
+ case 3:
+ return 1;
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ gen_op_iwmmxt_set_cup();
+ break;
+ case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
+ case 0x214: case 0x614: case 0xa14: case 0xe14:
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ if (gen_iwmmxt_shift(insn, 0xff))
+ return 1;
+ switch ((insn >> 22) & 3) {
+ case 0:
+ return 1;
+ case 1:
+ gen_op_iwmmxt_srlw_M0_T0();
+ break;
+ case 2:
+ gen_op_iwmmxt_srll_M0_T0();
+ break;
+ case 3:
+ gen_op_iwmmxt_srlq_M0_T0();
+ break;
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ gen_op_iwmmxt_set_cup();
+ break;
+ case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
+ case 0x014: case 0x414: case 0x814: case 0xc14:
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ if (gen_iwmmxt_shift(insn, 0xff))
+ return 1;
+ switch ((insn >> 22) & 3) {
+ case 0:
+ return 1;
+ case 1:
+ gen_op_iwmmxt_sraw_M0_T0();
+ break;
+ case 2:
+ gen_op_iwmmxt_sral_M0_T0();
+ break;
+ case 3:
+ gen_op_iwmmxt_sraq_M0_T0();
+ break;
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ gen_op_iwmmxt_set_cup();
+ break;
+ case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
+ case 0x114: case 0x514: case 0x914: case 0xd14:
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ if (gen_iwmmxt_shift(insn, 0xff))
+ return 1;
+ switch ((insn >> 22) & 3) {
+ case 0:
+ return 1;
+ case 1:
+ gen_op_iwmmxt_sllw_M0_T0();
+ break;
+ case 2:
+ gen_op_iwmmxt_slll_M0_T0();
+ break;
+ case 3:
+ gen_op_iwmmxt_sllq_M0_T0();
+ break;
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ gen_op_iwmmxt_set_cup();
+ break;
+ case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
+ case 0x314: case 0x714: case 0xb14: case 0xf14:
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ switch ((insn >> 22) & 3) {
+ case 0:
+ return 1;
+ case 1:
+ if (gen_iwmmxt_shift(insn, 0xf))
+ return 1;
+ gen_op_iwmmxt_rorw_M0_T0();
+ break;
+ case 2:
+ if (gen_iwmmxt_shift(insn, 0x1f))
+ return 1;
+ gen_op_iwmmxt_rorl_M0_T0();
+ break;
+ case 3:
+ if (gen_iwmmxt_shift(insn, 0x3f))
+ return 1;
+ gen_op_iwmmxt_rorq_M0_T0();
+ break;
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ gen_op_iwmmxt_set_cup();
+ break;
+ case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
+ case 0x916: case 0xb16: case 0xd16: case 0xf16:
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ rd1 = (insn >> 0) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ switch ((insn >> 22) & 3) {
+ case 0:
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_minsb_M0_wRn(rd1);
+ else
+ gen_op_iwmmxt_minub_M0_wRn(rd1);
+ break;
+ case 1:
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_minsw_M0_wRn(rd1);
+ else
+ gen_op_iwmmxt_minuw_M0_wRn(rd1);
+ break;
+ case 2:
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_minsl_M0_wRn(rd1);
+ else
+ gen_op_iwmmxt_minul_M0_wRn(rd1);
+ break;
+ case 3:
+ return 1;
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ break;
+ case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
+ case 0x816: case 0xa16: case 0xc16: case 0xe16:
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ rd1 = (insn >> 0) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ switch ((insn >> 22) & 3) {
+ case 0:
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_maxsb_M0_wRn(rd1);
+ else
+ gen_op_iwmmxt_maxub_M0_wRn(rd1);
+ break;
+ case 1:
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_maxsw_M0_wRn(rd1);
+ else
+ gen_op_iwmmxt_maxuw_M0_wRn(rd1);
+ break;
+ case 2:
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_maxsl_M0_wRn(rd1);
+ else
+ gen_op_iwmmxt_maxul_M0_wRn(rd1);
+ break;
+ case 3:
+ return 1;
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ break;
+ case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
+ case 0x402: case 0x502: case 0x602: case 0x702:
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ rd1 = (insn >> 0) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ gen_op_movl_T0_im((insn >> 20) & 3);
+ gen_op_iwmmxt_align_M0_T0_wRn(rd1);
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ break;
+ case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
+ case 0x41a: case 0x51a: case 0x61a: case 0x71a:
+ case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
+ case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ rd1 = (insn >> 0) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ switch ((insn >> 20) & 0xf) {
+ case 0x0:
+ gen_op_iwmmxt_subnb_M0_wRn(rd1);
+ break;
+ case 0x1:
+ gen_op_iwmmxt_subub_M0_wRn(rd1);
+ break;
+ case 0x3:
+ gen_op_iwmmxt_subsb_M0_wRn(rd1);
+ break;
+ case 0x4:
+ gen_op_iwmmxt_subnw_M0_wRn(rd1);
+ break;
+ case 0x5:
+ gen_op_iwmmxt_subuw_M0_wRn(rd1);
+ break;
+ case 0x7:
+ gen_op_iwmmxt_subsw_M0_wRn(rd1);
+ break;
+ case 0x8:
+ gen_op_iwmmxt_subnl_M0_wRn(rd1);
+ break;
+ case 0x9:
+ gen_op_iwmmxt_subul_M0_wRn(rd1);
+ break;
+ case 0xb:
+ gen_op_iwmmxt_subsl_M0_wRn(rd1);
+ break;
+ default:
+ return 1;
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ gen_op_iwmmxt_set_cup();
+ break;
+ case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
+ case 0x41e: case 0x51e: case 0x61e: case 0x71e:
+ case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
+ case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ gen_op_movl_T0_im(((insn >> 16) & 0xf0) | (insn & 0x0f));
+ gen_op_iwmmxt_shufh_M0_T0();
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ gen_op_iwmmxt_set_cup();
+ break;
+ case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
+ case 0x418: case 0x518: case 0x618: case 0x718:
+ case 0x818: case 0x918: case 0xa18: case 0xb18:
+ case 0xc18: case 0xd18: case 0xe18: case 0xf18:
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ rd1 = (insn >> 0) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ switch ((insn >> 20) & 0xf) {
+ case 0x0:
+ gen_op_iwmmxt_addnb_M0_wRn(rd1);
+ break;
+ case 0x1:
+ gen_op_iwmmxt_addub_M0_wRn(rd1);
+ break;
+ case 0x3:
+ gen_op_iwmmxt_addsb_M0_wRn(rd1);
+ break;
+ case 0x4:
+ gen_op_iwmmxt_addnw_M0_wRn(rd1);
+ break;
+ case 0x5:
+ gen_op_iwmmxt_adduw_M0_wRn(rd1);
+ break;
+ case 0x7:
+ gen_op_iwmmxt_addsw_M0_wRn(rd1);
+ break;
+ case 0x8:
+ gen_op_iwmmxt_addnl_M0_wRn(rd1);
+ break;
+ case 0x9:
+ gen_op_iwmmxt_addul_M0_wRn(rd1);
+ break;
+ case 0xb:
+ gen_op_iwmmxt_addsl_M0_wRn(rd1);
+ break;
+ default:
+ return 1;
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ gen_op_iwmmxt_set_cup();
+ break;
+ case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
+ case 0x408: case 0x508: case 0x608: case 0x708:
+ case 0x808: case 0x908: case 0xa08: case 0xb08:
+ case 0xc08: case 0xd08: case 0xe08: case 0xf08:
+ wrd = (insn >> 12) & 0xf;
+ rd0 = (insn >> 16) & 0xf;
+ rd1 = (insn >> 0) & 0xf;
+ gen_op_iwmmxt_movq_M0_wRn(rd0);
+ if (!(insn & (1 << 20)))
+ return 1;
+ switch ((insn >> 22) & 3) {
+ case 0:
+ return 1;
+ case 1:
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_packsw_M0_wRn(rd1);
+ else
+ gen_op_iwmmxt_packuw_M0_wRn(rd1);
+ break;
+ case 2:
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_packsl_M0_wRn(rd1);
+ else
+ gen_op_iwmmxt_packul_M0_wRn(rd1);
+ break;
+ case 3:
+ if (insn & (1 << 21))
+ gen_op_iwmmxt_packsq_M0_wRn(rd1);
+ else
+ gen_op_iwmmxt_packuq_M0_wRn(rd1);
+ break;
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ gen_op_iwmmxt_set_cup();
+ break;
+ case 0x201: case 0x203: case 0x205: case 0x207:
+ case 0x209: case 0x20b: case 0x20d: case 0x20f:
+ case 0x211: case 0x213: case 0x215: case 0x217:
+ case 0x219: case 0x21b: case 0x21d: case 0x21f:
+ wrd = (insn >> 5) & 0xf;
+ rd0 = (insn >> 12) & 0xf;
+ rd1 = (insn >> 0) & 0xf;
+ if (rd0 == 0xf || rd1 == 0xf)
+ return 1;
+ gen_op_iwmmxt_movq_M0_wRn(wrd);
+ switch ((insn >> 16) & 0xf) {
+ case 0x0: /* TMIA */
+ gen_op_movl_TN_reg[0][rd0]();
+ gen_op_movl_TN_reg[1][rd1]();
+ gen_op_iwmmxt_muladdsl_M0_T0_T1();
+ break;
+ case 0x8: /* TMIAPH */
+ gen_op_movl_TN_reg[0][rd0]();
+ gen_op_movl_TN_reg[1][rd1]();
+ gen_op_iwmmxt_muladdsw_M0_T0_T1();
+ break;
+ case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
+ gen_op_movl_TN_reg[1][rd0]();
+ if (insn & (1 << 16))
+ gen_op_shrl_T1_im(16);
+ gen_op_movl_T0_T1();
+ gen_op_movl_TN_reg[1][rd1]();
+ if (insn & (1 << 17))
+ gen_op_shrl_T1_im(16);
+ gen_op_iwmmxt_muladdswl_M0_T0_T1();
+ break;
+ default:
+ return 1;
+ }
+ gen_op_iwmmxt_movq_wRn_M0(wrd);
+ gen_op_iwmmxt_set_mup();
+ break;
+ default:
+ return 1;
+ }
+
+ return 0;
+}
+
+/* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
+ (ie. an undefined instruction). */
+static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
+{
+ int acc, rd0, rd1, rdhi, rdlo;
+
+ if ((insn & 0x0ff00f10) == 0x0e200010) {
+ /* Multiply with Internal Accumulate Format */
+ rd0 = (insn >> 12) & 0xf;
+ rd1 = insn & 0xf;
+ acc = (insn >> 5) & 7;
+
+ if (acc != 0)
+ return 1;
+
+ switch ((insn >> 16) & 0xf) {
+ case 0x0: /* MIA */
+ gen_op_movl_TN_reg[0][rd0]();
+ gen_op_movl_TN_reg[1][rd1]();
+ gen_op_iwmmxt_muladdsl_M0_T0_T1();
+ break;
+ case 0x8: /* MIAPH */
+ gen_op_movl_TN_reg[0][rd0]();
+ gen_op_movl_TN_reg[1][rd1]();
+ gen_op_iwmmxt_muladdsw_M0_T0_T1();
+ break;
+ case 0xc: /* MIABB */
+ case 0xd: /* MIABT */
+ case 0xe: /* MIATB */
+ case 0xf: /* MIATT */
+ gen_op_movl_TN_reg[1][rd0]();
+ if (insn & (1 << 16))
+ gen_op_shrl_T1_im(16);
+ gen_op_movl_T0_T1();
+ gen_op_movl_TN_reg[1][rd1]();
+ if (insn & (1 << 17))
+ gen_op_shrl_T1_im(16);
+ gen_op_iwmmxt_muladdswl_M0_T0_T1();
+ break;
+ default:
+ return 1;
+ }
+
+ gen_op_iwmmxt_movq_wRn_M0(acc);
+ return 0;
+ }
+
+ if ((insn & 0x0fe00ff8) == 0x0c400000) {
+ /* Internal Accumulator Access Format */
+ rdhi = (insn >> 16) & 0xf;
+ rdlo = (insn >> 12) & 0xf;
+ acc = insn & 7;
+
+ if (acc != 0)
+ return 1;
+
+ if (insn & ARM_CP_RW_BIT) { /* MRA */
+ gen_op_iwmmxt_movl_T0_T1_wRn(acc);
+ gen_op_movl_reg_TN[0][rdlo]();
+ gen_op_movl_T0_im((1 << (40 - 32)) - 1);
+ gen_op_andl_T0_T1();
+ gen_op_movl_reg_TN[0][rdhi]();
+ } else { /* MAR */
+ gen_op_movl_TN_reg[0][rdlo]();
+ gen_op_movl_TN_reg[1][rdhi]();
+ gen_op_iwmmxt_movl_wRn_T0_T1(acc);
+ }
+ return 0;
+ }
+
+ return 1;
+}
+
/* Disassemble system coprocessor instruction. Return nonzero if
instruction is not defined. */
static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
return 1;
}
- if (insn & (1 << 20)) {
+ if (insn & ARM_CP_RW_BIT) {
if (!env->cp[cp].cp_read)
return 1;
gen_op_movl_T0_im((uint32_t) s->pc);
return 0;
}
rd = (insn >> 12) & 0xf;
- if (insn & (1 << 20)) {
+ if (insn & ARM_CP_RW_BIT) {
gen_op_movl_T0_cp15(insn);
/* If the destination register is r15 then sets condition codes. */
if (rd != 15)
we only set half the register. */
gen_mov_F0_vreg(1, rn);
gen_op_vfp_mrrd();
- if (insn & (1 << 20)) {
+ if (insn & ARM_CP_RW_BIT) {
/* vfp->arm */
if (insn & (1 << 21))
gen_movl_reg_T1(s, rd);
}
} else {
rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
- if (insn & (1 << 20)) {
+ if (insn & ARM_CP_RW_BIT) {
/* vfp->arm */
if (insn & (1 << 21)) {
/* system register */
} else
rm = ((insn << 1) & 0x1e) | ((insn >> 5) & 1);
- if (insn & (1 << 20)) {
+ if (insn & ARM_CP_RW_BIT) {
/* vfp->arm */
if (dp) {
gen_mov_F0_vreg(1, rm);
else
offset = 4;
for (i = 0; i < n; i++) {
- if (insn & (1 << 20)) {
+ if (insn & ARM_CP_RW_BIT) {
/* load */
gen_vfp_ld(s, dp);
gen_mov_vreg_F0(dp, rd + i);
goto illegal_op;
switch (op1) {
case 0 ... 1:
+ if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
+ if (disas_iwmmxt_insn(env, s, insn))
+ goto illegal_op;
+ } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
+ if (disas_dsp_insn(env, s, insn))
+ goto illegal_op;
+ } else
+ goto illegal_op;
+ break;
case 2 ... 9:
case 12 ... 14:
if (disas_cp_insn (env, s, insn))
projects / mirror_qemu.git / commitdiff