if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
- if (value <= plic->num_priorities) {
+ if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
+ /*
+ * if "num_priorities + 1" is power-of-2, make each register bit of
+ * interrupt priority WARL (Write-Any-Read-Legal). Just filter
+ * out the access to unsupported priority bits.
+ */
+ plic->source_priority[irq] = value % (plic->num_priorities + 1);
+ sifive_plic_update(plic);
+ } else if (value <= plic->num_priorities) {
plic->source_priority[irq] = value;
sifive_plic_update(plic);
}
uint32_t contextid = (addr & (plic->context_stride - 1));
if (contextid == 0) {
- if (value <= plic->num_priorities) {
+ if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
+ /*
+ * if "num_priorities + 1" is power-of-2, each register bit of
+ * interrupt priority is WARL (Write-Any-Read-Legal). Just
+ * filter out the access to unsupported priority bits.
+ */
+ plic->target_priority[addrid] = value %
+ (plic->num_priorities + 1);
+ sifive_plic_update(plic);
+ } else if (value <= plic->num_priorities) {
plic->target_priority[addrid] = value;
sifive_plic_update(plic);
}